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authorDaniel Vetter <daniel.vetter@ffwll.ch>2011-03-25 21:53:07 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2011-03-25 21:53:07 +0100
commit2aac22358feb217435bb4b77ae824db823435db0 (patch)
tree85197b3c1762f12516e28d5d34daa096d50f8746 /tests
parentcfba9dd371bdf8031bf2bd77817a7a7976319e61 (diff)
gem_stress: implement gen5 blitter work-around
ddx and mesa assume that this is issued after every blit command. Breaking that invariant results in a dying gpu. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tests')
-rw-r--r--tests/gem_stress.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/gem_stress.c b/tests/gem_stress.c
index 1a31ab32..62e91c0e 100644
--- a/tests/gem_stress.c
+++ b/tests/gem_stress.c
@@ -66,6 +66,8 @@
#include "intel_batchbuffer.h"
#include "intel_gpu_tools.h"
+#define CMD_POLY_STIPPLE_OFFSET 0x7906
+
/** TODO:
* - beat on relaxed fencing (i.e. mappable/fenceable tracking in the kernel)
* - render copy (to check fence tracking and cache coherency management by the
@@ -164,6 +166,13 @@ static void keep_gpu_busy(void)
OUT_BATCH(src_pitch);
OUT_RELOC(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
ADVANCE_BATCH();
+
+ if (IS_GEN5(devid)) {
+ BEGIN_BATCH(2);
+ OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ }
}
static unsigned int copyfunc_seq = 0;
@@ -279,6 +288,13 @@ static void blitter_copyfunc(struct scratch_buf *src, unsigned src_x, unsigned s
OUT_RELOC(src->bo, I915_GEM_DOMAIN_RENDER, 0, 0);
ADVANCE_BATCH();
+ if (IS_GEN5(devid)) {
+ BEGIN_BATCH(2);
+ OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ }
+
if (!(keep_gpu_busy_counter & 1) && !fence_storm)
keep_gpu_busy();