tests: adapt storedw tests to ppgtt

MI_MEM_VIRTUAL actually means use global gtt now, not setting the bit
means use ppgtt. On previous gens, not setting the bits ment 'use
physical memory'. So what, the usual confusion.

Note that for some odd reasong this is broken on gen6, but only on the
bsd ring. Unexpected.

Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

4 files changed, 40 insertions, 8 deletions

diff --git a/tests/gem_storedw_batches_loop.c b/tests/gem_storedw_batches_loop.c
index 23c61790..8cf5f719 100644
--- a/tests/gem_storedw_batches_loop.c
+++ b/tests/gem_storedw_batches_loop.c
@@ -44,6 +44,7 @@
 
 static drm_intel_bufmgr *bufmgr;
 static drm_intel_bo *target_bo;
+static int has_ppgtt = 0;
 
 /* Like the store dword test, but we create new command buffers each time */
 static void
@@ -53,7 +54,9 @@ store_dword_loop(void)
 	uint32_t *buf;
 	drm_intel_bo *cmd_bo;
 
-	cmd = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
+	cmd = MI_STORE_DWORD_IMM;
+	if (!has_ppgtt)
+		cmd |= MI_MEM_VIRTUAL;
 
 	for (i = 0; i < 0x80000; i++) {
 		cmd_bo = drm_intel_bo_alloc(bufmgr, "cmd bo", 4096, 4096);
@@ -136,6 +139,8 @@ int main(int argc, char **argv)
 	fd = drm_open_any();
 	devid = intel_get_drm_devid(fd);
 
+	has_ppgtt = gem_uses_aliasing_ppgtt(fd);
+
 	if (IS_GEN2(devid) || IS_GEN3(devid) || IS_GEN4(devid) || IS_GEN5(devid)) {
 
 		fprintf(stderr, "MI_STORE_DATA can only use GTT address on gen4+/g33 and"
diff --git a/tests/gem_storedw_loop_blt.c b/tests/gem_storedw_loop_blt.c
index 88b12d37..dda9b835 100644
--- a/tests/gem_storedw_loop_blt.c
+++ b/tests/gem_storedw_loop_blt.c
@@ -45,6 +45,7 @@
 static drm_intel_bufmgr *bufmgr;
 struct intel_batchbuffer *batch;
 static drm_intel_bo *target_buffer;
+static int has_ppgtt = 0;
 
 /*
  * Testcase: Basic blitter MI check using MI_STORE_DATA_IMM
@@ -56,7 +57,9 @@ store_dword_loop(void)
 	int cmd, i, val = 0;
 	uint32_t *buf;
 
-	cmd = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
+	cmd = MI_STORE_DWORD_IMM;
+	if (!has_ppgtt)
+		cmd |= MI_MEM_VIRTUAL;
 
 	for (i = 0; i < 0x100000; i++) {
 		BEGIN_BATCH(4);
@@ -105,6 +108,8 @@ int main(int argc, char **argv)
 	fd = drm_open_any();
 	devid = intel_get_drm_devid(fd);
 
+	has_ppgtt = gem_uses_aliasing_ppgtt(fd);
+
 	if (IS_GEN2(devid) || IS_GEN3(devid) || IS_GEN4(devid) || IS_GEN5(devid)) {
 
 		fprintf(stderr, "MI_STORE_DATA can only use GTT address on gen4+/g33 and "
@@ -112,8 +117,11 @@ int main(int argc, char **argv)
 		return 77;
 	}
 
-	/* This supposedly only works with ppgtt */
-	return 77;
+	/* This only works with ppgtt */
+	if (!has_ppgtt) {
+		fprintf(stderr, "no ppgtt detected, which is required\n");
+		return 77;
+	}
 
 	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 	if (!bufmgr) {
diff --git a/tests/gem_storedw_loop_bsd.c b/tests/gem_storedw_loop_bsd.c
index 09351e2f..d7c61047 100644
--- a/tests/gem_storedw_loop_bsd.c
+++ b/tests/gem_storedw_loop_bsd.c
@@ -45,6 +45,7 @@
 static drm_intel_bufmgr *bufmgr;
 struct intel_batchbuffer *batch;
 static drm_intel_bo *target_buffer;
+static int has_ppgtt = 0;
 
 /*
  * Testcase: Basic bsd MI check using MI_STORE_DATA_IMM
@@ -56,7 +57,9 @@ store_dword_loop(void)
 	int cmd, i, val = 0;
 	uint32_t *buf;
 
-	cmd = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
+	cmd = MI_STORE_DWORD_IMM;
+	if (!has_ppgtt)
+		cmd |= MI_MEM_VIRTUAL;
 
 	for (i = 0; i < 0x100000; i++) {
 		BEGIN_BATCH(4);
@@ -105,6 +108,8 @@ int main(int argc, char **argv)
 	fd = drm_open_any();
 	devid = intel_get_drm_devid(fd);
 
+	has_ppgtt = gem_uses_aliasing_ppgtt(fd);
+
 	if (IS_GEN2(devid) || IS_GEN3(devid) || IS_GEN4(devid) || IS_GEN5(devid)) {
 
 		fprintf(stderr, "MI_STORE_DATA can only use GTT address on gen4+/g33 and "
@@ -112,8 +117,17 @@ int main(int argc, char **argv)
 		return 77;
 	}
 
-	/* This supposedly only works with ppgtt */
-	return 77;
+	if (IS_GEN6(devid)) {
+
+		fprintf(stderr, "MI_STORE_DATA broken on gen6 bsd\n");
+		return 77;
+	}
+
+	/* This only works with ppgtt */
+	if (!has_ppgtt) {
+		fprintf(stderr, "no ppgtt detected, which is required\n");
+		return 77;
+	}
 
 	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
 	if (!bufmgr) {
diff --git a/tests/gem_storedw_loop_render.c b/tests/gem_storedw_loop_render.c
index b3b74173..19a41b65 100644
--- a/tests/gem_storedw_loop_render.c
+++ b/tests/gem_storedw_loop_render.c
@@ -45,6 +45,7 @@
 static drm_intel_bufmgr *bufmgr;
 struct intel_batchbuffer *batch;
 static drm_intel_bo *target_buffer;
+static int has_ppgtt = 0;
 
 /*
  * Testcase: Basic render MI check using MI_STORE_DATA_IMM
@@ -56,7 +57,9 @@ store_dword_loop(void)
 	int cmd, i, val = 0;
 	uint32_t *buf;
 
-	cmd = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
+	cmd = MI_STORE_DWORD_IMM;
+	if (!has_ppgtt)
+		cmd |= MI_MEM_VIRTUAL;
 
 	for (i = 0; i < 0x100000; i++) {
 		BEGIN_BATCH(4);
@@ -105,6 +108,8 @@ int main(int argc, char **argv)
 	fd = drm_open_any();
 	devid = intel_get_drm_devid(fd);
 
+	has_ppgtt = gem_uses_aliasing_ppgtt(fd);
+
 	if (IS_GEN2(devid) || IS_GEN3(devid) || IS_GEN4(devid) || IS_GEN5(devid)) {
 
 		fprintf(stderr, "MI_STORE_DATA can only use GTT address on gen4+/g33 and "