diff options
author | Thomas Wood <thomas.wood@intel.com> | 2015-08-25 11:30:11 +0100 |
---|---|---|
committer | Thomas Wood <thomas.wood@intel.com> | 2015-09-08 16:14:45 +0100 |
commit | af9791849467a3437e0920c8f08c5a646302da7d (patch) | |
tree | 3f9780d54a2f52bf76823b76257713f4bbc607aa /tools/registers/vlv_pipe_b.txt | |
parent | 2142a15d49f85175677ff360833869afe9c79b58 (diff) |
tools: remove quick_dump
Remove quick_dump as it has been replaced by the intel_reg tool and move
the register definition files to tools/registers.
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'tools/registers/vlv_pipe_b.txt')
-rw-r--r-- | tools/registers/vlv_pipe_b.txt | 174 |
1 files changed, 174 insertions, 0 deletions
diff --git a/tools/registers/vlv_pipe_b.txt b/tools/registers/vlv_pipe_b.txt new file mode 100644 index 00000000..de5e9681 --- /dev/null +++ b/tools/registers/vlv_pipe_b.txt @@ -0,0 +1,174 @@ +('PIPEB_DSL', '0x71000', '0x180000') +('PIPEB_SLC', '0x71004', '0x180000') +('PIPEBCONF', '0x71008', '0x180000') +('PIPEBGCMAXRED', '0x71010', '0x180000') +('PIPEBGCMAXGREEN', '0x71014', '0x180000') +('PIPEBGCMAXBLUE', '0x71018', '0x180000') +('PIPEBSTAT', '0x71024', '0x180000') +('PIPEBFRAMECOUNT', '0x71040', '0x180000') +('PIPEBFLIPCOUNT', '0x71044', '0x180000') +('PIPEBMSAMISC', '0x71048', '0x180000') + +('DSPBADDR', '0x7117C', '0x180000') +('DSPBCNTR', '0x71180', '0x180000') +('DSPBLINOFF', '0x71184', '0x180000') +('DSPBSTRIDE', '0x71188', '0x180000') +('DSPBKEYVAL', '0x71194', '0x180000') +('DSPBKEYMSK', '0x71198', '0x180000') +('DSPBSURF', '0x7119C', '0x180000') +('DSPBTILEOFF', '0x711A4', '0x180000') +('DSPBSURFLIVE', '0x711AC', '0x180000') +('DSPBFLPQSTAT', '0x71200', '0x180000') + +('CURBCNTR', '0x700C0', '0x180000') +('CURBBASE', '0x700C4', '0x180000') +('CURBPOS', '0x700C8', '0x180000') +('CURBRESV', '0x700CC', '0x180000') +('CURBPALET0', '0x700D0', '0x180000') +('CURBPALET1', '0x700D4', '0x180000') +('CURBPALET2', '0x700D8', '0x180000') +('CURBPALET3', '0x700DC', '0x180000') +('CURBLIVEBASE', '0x700EC', '0x180000') + +('SPCCNTR', '0x72380', '0x180000') +('SPCLINOFF', '0x72384', '0x180000') +('SPCSTRIDE', '0x72388', '0x180000') +('SPCPOS', '0x7238C', '0x180000') +('SPCSIZE', '0x72390', '0x180000') +('SPCKEYMINVAL', '0x72394', '0x180000') +('SPCKEYMSK', '0x72398', '0x180000') +('SPCSURF', '0x7239C', '0x180000') +('SPCKEYMAXVAL', '0x723A0', '0x180000') +('SPCTILEOFF', '0x723A4', '0x180000') +('SPCCONTALPHA', '0x723A8', '0x180000') +('SPCLIVESURF', '0x723AC', '0x180000') +('SPCCLRC0', '0x723D0', '0x180000') +('SPCCLRC1', '0x723D4', '0x180000') +('SPCGAMC5', '0x723E0', '0x180000') +('SPCGAMC4', '0x723E4', '0x180000') +('SPCGAMC3', '0x723E8', '0x180000') +('SPCGAMC2', '0x723EC', '0x180000') +('SPCGAMC1', '0x723F0', '0x180000') +('SPCGAMC0', '0x723F4', '0x180000') + +('SPDCNTR', '0x72480', '0x180000') +('SPDLINOFF', '0x72484', '0x180000') +('SPDSTRIDE', '0x72488', '0x180000') +('SPDPOS', '0x7248C', '0x180000') +('SPDSIZE', '0x72490', '0x180000') +('SPDKEYMINVAL', '0x72494', '0x180000') +('SPDKEYMSK', '0x72498', '0x180000') +('SPDSURF', '0x7249C', '0x180000') +('SPDKEYMAXVAL', '0x724A0', '0x180000') +('SPDTILEOFF', '0x724A4', '0x180000') +('SPDCONTALPHA', '0x724A8', '0x180000') +('SPDLIVESURF', '0x724AC', '0x180000') +('SPDCLRC0', '0x724D0', '0x180000') +('SPDCLRC1', '0x724D4', '0x180000') +('SPDGAMC5', '0x724E0', '0x180000') +('SPDGAMC4', '0x724E4', '0x180000') +('SPDGAMC3', '0x724E8', '0x180000') +('SPDGAMC2', '0x724EC', '0x180000') +('SPDGAMC1', '0x724F0', '0x180000') +('SPDGAMC0', '0x724F4', '0x180000') + +('DPALETTE_B', '0xA800', '0x180000') +('DPLLB_CTRL', '0x6018', '0x180000') +('DPLLBMD', '0x6020', '0x180000') + +('HTOTAL_B', '0x61000', '0x180000') +('HBLANK_B', '0x61004', '0x180000') +('HSYNC_B', '0x61008', '0x180000') +('VTOTAL_B', '0x6100C', '0x180000') +('VBLANK_B', '0x61010', '0x180000') +('VSYNC_B', '0x61014', '0x180000') +('PIPEBSRC', '0x6101C', '0x180000') +('BCLRPAT_B', '0x61020', '0x180000') +('VSYNCSHIFT_B', '0x61028', '0x180000') + +('TRANSB_DATA_M1', '0x61030', '0x180000') +('TRANSB_DATA_N1', '0x61034', '0x180000') +('TRANSB_DATA_M2', '0x61038', '0x180000') +('TRANSB_DATA_N2', '0x6103C', '0x180000') +('TRANSB_LINK_M1', '0x61040', '0x180000') +('TRANSB_LINK_N1', '0x61044', '0x180000') +('TRANSB_LINK_M2', '0x61048', '0x180000') +('TRANSB_LINK_N2', '0x6104C', '0x180000') + +('CRC_CTRL_RED_B', '0x61050', '0x180000') +('CRC_CTRL_GREEN_B', '0x61054', '0x180000') +('CRC_CTRL_BLUE_B', '0x61058', '0x180000') +('CRC_CTRL_ALPHA_B', '0x6105C', '0x180000') +('CRC_CTRL_RESIDUE2_B', '0x61070', '0x180000') +('CRC_RES_RED_B', '0x61060', '0x180000') +('CRC_RES_GREEN_B', '0x61064', '0x180000') +('CRC_RES_BLUE_V', '0x61068', '0x180000') +('CRC_RES_ALPHAB', '0x6106C', '0x180000') +('CRC_RES_RESIDUAL2_B', '0x61080', '0x180000') + +('PSRCTLB', '0x61090', '0x180000') +('PSRSTATB', '0x61094', '0x180000') +('PSRCRC1B', '0x61098', '0x180000') +('PSRCRC2B', '0x6109C', '0x180000') +('VSCSDPB', '0x610A0', '0x180000') + +('PIPEB_WGCC_C01_C00', '0x610B0', '0x180000') +('PIPEB_WGCC_C02', '0x610B4', '0x180000') +('PIPEB_WGCC_C11_C10', '0x610B8', '0x180000') +('PIPEB_WGCC_C12', '0x610BC', '0x180000') +('PIPEB_WGCC_C21_C20', '0x610C0', '0x180000') +('PIPEB_WGCC_C22', '0x610C4', '0x180000') + +('VIDEO_DIP_CTL_B', '0x61170', '0x180000') +('VIDEO_DIP_DATA_B', '0x61174', '0x180000') +('VIDEO_DIP_GDCP_PAYLOAD_B', '0x61178', '0x180000') + +('PIPEB_CGM_DEGAMMA', '0x68000', '0x180000') +('PIPEB_CGM_GAMMA', '0x69000', '0x180000') +('PIPEB_CGM_CSC_COEFF01', '0x69900', '0x180000') +('PIPEB_CGM_CSC_COEFF23', '0x69904', '0x180000') +('PIPEB_CGM_CSC_COEFF45', '0x69908', '0x180000') +('PIPEB_CGM_CSC_COEFF67', '0x6990C', '0x180000') +('PIPEB_CGM_CSC_COEFF8', '0x69910', '0x180000') +('PIPEB_CGM_CONTROL', '0x69A00', '0x180000') + +('PIPEB_PP_STATUS', '0x61300', '0x180000') +('PIPEB_PP_CONTROL', '0x61304', '0x180000') +('PIPEB_PP_ON_DELAYS', '0x61308', '0x180000') +('PIPEB_PP_OFF_DELAYS', '0x6130C', '0x180000') +('PIPEB_PP_DIVISOR', '0x61310', '0x180000') + +('PIPEB_BLC_PWM_CLT2', '0x61350', '0x180000') +('PIPEB_BLC_PWM_CTL', '0x61354', '0x180000') +('PIPEB_BLM_HIST_CTL', '0x61360', '0x180000') +('PIPEB_IMG_ENH_BIN_DATA', '0x61364', '0x180000') +('PIPEB_HIST_THRESH_GUARD', '0x61368', '0x180000') + +('AUD_CONFIG_B', '0x62100', '0x180000') +('AUD_MISC_CTRL_B', '0x62110', '0x180000') +('AUD_CTS_ENABLE_B', '0x62128', '0x180000') +('AUD_HDMIW_HDMIEDID_B', '0x62150', '0x180000') +('AUD_HDMIW_INFOFR_B', '0x62154', '0x180000') +('AUD_OUT_DIG_CNVT_B', '0x62180', '0x180000') +('AUD_OUT_STR_DESC_B', '0x62184', '0x180000') +('AUD_CNTL_ST_B', '0x621B4', '0x180000') +('AUD_OUT_DIG_CNVTB_DBG', '0x62F44', '0x180000') + +('STREAM_B_LPE_AUD_CONFIG', '0x65800', '0x180000') +('STREAM_B_LPE_AUD_CH_STATUS_0', '0x65808', '0x180000') +('STREAM_B_LPE_AUD_CH_STATUS_1', '0x6580C', '0x180000') +('STREAM_B_LPE_AUD_HDMI_CTS_DP_MAUD', '0x65810', '0x180000') +('STREAM_B_LPE_AUD_HDMI_N_DP_NAUD', '0x65814', '0x180000') +('STREAM_B_LPE_AUD_BUFFER_CONFIG', '0x65820', '0x180000') +('STREAM_B_LPE_AUD_BUF_CH_SWP', '0x65824', '0x180000') +('STREAM_B_LPE_AUD_BUF_A_ADDR', '0x65840', '0x180000') +('STREAM_B_LPE_AUD_BUF_A_LENGTH', '0x65844', '0x180000') +('STREAM_B_LPE_AUD_BUF_B_ADDR', '0x65848', '0x180000') +('STREAM_B_LPE_AUD_BUF_B_LENGTH', '0x6584C', '0x180000') +('STREAM_B_LPE_AUD_BUF_C_ADDR', '0x65850', '0x180000') +('STREAM_B_LPE_AUD_BUF_C_LENGTH', '0x65854', '0x180000') +('STREAM_B_LPE_AUD_BUF_D_ADDR', '0x65858', '0x180000') +('STREAM_B_LPE_AUD_BUF_D_LENGTH', '0x6585C', '0x180000') +('STREAM_B_LPE_AUD_CNTL_ST', '0x65860', '0x180000') +('STREAM_B_LPE_AUD_HDMI_STATUS', '0x65864', '0x180000') +('STREAM_B_LPE_AUD_HDMIW_INFOFR', '0x65868', '0x180000') |