diff options
Diffstat (limited to 'assembler/src')
| -rw-r--r-- | assembler/src/Makefile.am | 11 | ||||
| -rw-r--r-- | assembler/src/brw_defines.h | 846 | ||||
| -rw-r--r-- | assembler/src/brw_structs.h | 1327 | ||||
| -rw-r--r-- | assembler/src/gen4asm.h | 103 | ||||
| -rw-r--r-- | assembler/src/gram.y | 1322 | ||||
| -rw-r--r-- | assembler/src/lex.l | 324 | ||||
| -rw-r--r-- | assembler/src/main.c | 100 |
7 files changed, 4033 insertions, 0 deletions
diff --git a/assembler/src/Makefile.am b/assembler/src/Makefile.am new file mode 100644 index 00000000..737e9367 --- /dev/null +++ b/assembler/src/Makefile.am @@ -0,0 +1,11 @@ +bin_PROGRAMS = gen4asm + +gen4asm_SOURCES = \ + brw_defines.h \ + brw_structs.h \ + gen4asm.h \ + gram.y \ + lex.l \ + main.c + +# man_MANS = gen4asm.1 diff --git a/assembler/src/brw_defines.h b/assembler/src/brw_defines.h new file mode 100644 index 00000000..4ec02246 --- /dev/null +++ b/assembler/src/brw_defines.h @@ -0,0 +1,846 @@ + /************************************************************************** + * + * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#ifndef BRW_DEFINES_H +#define BRW_DEFINES_H + +/* + */ +#define MI_NOOP 0x00 +#define MI_USER_INTERRUPT 0x02 +#define MI_WAIT_FOR_EVENT 0x03 +#define MI_FLUSH 0x04 +#define MI_REPORT_HEAD 0x07 +#define MI_ARB_ON_OFF 0x08 +#define MI_BATCH_BUFFER_END 0x0A +#define MI_OVERLAY_FLIP 0x11 +#define MI_LOAD_SCAN_LINES_INCL 0x12 +#define MI_LOAD_SCAN_LINES_EXCL 0x13 +#define MI_DISPLAY_BUFFER_INFO 0x14 +#define MI_SET_CONTEXT 0x18 +#define MI_STORE_DATA_IMM 0x20 +#define MI_STORE_DATA_INDEX 0x21 +#define MI_LOAD_REGISTER_IMM 0x22 +#define MI_STORE_REGISTER_MEM 0x24 +#define MI_BATCH_BUFFER_START 0x31 + +#define MI_SYNCHRONOUS_FLIP 0x0 +#define MI_ASYNCHRONOUS_FLIP 0x1 + +#define MI_BUFFER_SECURE 0x0 +#define MI_BUFFER_NONSECURE 0x1 + +#define MI_ARBITRATE_AT_CHAIN_POINTS 0x0 +#define MI_ARBITRATE_BETWEEN_INSTS 0x1 +#define MI_NO_ARBITRATION 0x3 + +#define MI_CONDITION_CODE_WAIT_DISABLED 0x0 +#define MI_CONDITION_CODE_WAIT_0 0x1 +#define MI_CONDITION_CODE_WAIT_1 0x2 +#define MI_CONDITION_CODE_WAIT_2 0x3 +#define MI_CONDITION_CODE_WAIT_3 0x4 +#define MI_CONDITION_CODE_WAIT_4 0x5 + +#define MI_DISPLAY_PIPE_A 0x0 +#define MI_DISPLAY_PIPE_B 0x1 + +#define MI_DISPLAY_PLANE_A 0x0 +#define MI_DISPLAY_PLANE_B 0x1 +#define MI_DISPLAY_PLANE_C 0x2 + +#define MI_STANDARD_FLIP 0x0 +#define MI_ENQUEUE_FLIP_PERFORM_BASE_FRAME_NUMBER_LOAD 0x1 +#define MI_ENQUEUE_FLIP_TARGET_FRAME_NUMBER_RELATIVE 0x2 +#define MI_ENQUEUE_FLIP_ABSOLUTE_TARGET_FRAME_NUMBER 0x3 + +#define MI_PHYSICAL_ADDRESS 0x0 +#define MI_VIRTUAL_ADDRESS 0x1 + +#define MI_BUFFER_MEMORY_MAIN 0x0 +#define MI_BUFFER_MEMORY_GTT 0x2 +#define MI_BUFFER_MEMORY_PER_PROCESS_GTT 0x3 + +#define MI_FLIP_CONTINUE 0x0 +#define MI_FLIP_ON 0x1 +#define MI_FLIP_OFF 0x2 + +#define MI_UNTRUSTED_REGISTER_SPACE 0x0 +#define MI_TRUSTED_REGISTER_SPACE 0x1 + +/* 3D state: + */ +#define _3DOP_3DSTATE_PIPELINED 0x0 +#define _3DOP_3DSTATE_NONPIPELINED 0x1 +#define _3DOP_3DCONTROL 0x2 +#define _3DOP_3DPRIMITIVE 0x3 + +#define _3DSTATE_PIPELINED_POINTERS 0x00 +#define _3DSTATE_BINDING_TABLE_POINTERS 0x01 +#define _3DSTATE_VERTEX_BUFFERS 0x08 +#define _3DSTATE_VERTEX_ELEMENTS 0x09 +#define _3DSTATE_INDEX_BUFFER 0x0A +#define _3DSTATE_VF_STATISTICS 0x0B +#define _3DSTATE_DRAWING_RECTANGLE 0x00 +#define _3DSTATE_CONSTANT_COLOR 0x01 +#define _3DSTATE_SAMPLER_PALETTE_LOAD 0x02 +#define _3DSTATE_CHROMA_KEY 0x04 +#define _3DSTATE_DEPTH_BUFFER 0x05 +#define _3DSTATE_POLY_STIPPLE_OFFSET 0x06 +#define _3DSTATE_POLY_STIPPLE_PATTERN 0x07 +#define _3DSTATE_LINE_STIPPLE 0x08 +#define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09 +#define _3DCONTROL 0x00 +#define _3DPRIMITIVE 0x00 + +#define PIPE_CONTROL_NOWRITE 0x00 +#define PIPE_CONTROL_WRITEIMMEDIATE 0x01 +#define PIPE_CONTROL_WRITEDEPTH 0x02 +#define PIPE_CONTROL_WRITETIMESTAMP 0x03 + +#define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00 +#define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01 + +#define _3DPRIM_POINTLIST 0x01 +#define _3DPRIM_LINELIST 0x02 +#define _3DPRIM_LINESTRIP 0x03 +#define _3DPRIM_TRILIST 0x04 +#define _3DPRIM_TRISTRIP 0x05 +#define _3DPRIM_TRIFAN 0x06 +#define _3DPRIM_QUADLIST 0x07 +#define _3DPRIM_QUADSTRIP 0x08 +#define _3DPRIM_LINELIST_ADJ 0x09 +#define _3DPRIM_LINESTRIP_ADJ 0x0A +#define _3DPRIM_TRILIST_ADJ 0x0B +#define _3DPRIM_TRISTRIP_ADJ 0x0C +#define _3DPRIM_TRISTRIP_REVERSE 0x0D +#define _3DPRIM_POLYGON 0x0E +#define _3DPRIM_RECTLIST 0x0F +#define _3DPRIM_LINELOOP 0x10 +#define _3DPRIM_POINTLIST_BF 0x11 +#define _3DPRIM_LINESTRIP_CONT 0x12 +#define _3DPRIM_LINESTRIP_BF 0x13 +#define _3DPRIM_LINESTRIP_CONT_BF 0x14 +#define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 + +#define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0 +#define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1 + +#define BRW_ANISORATIO_2 0 +#define BRW_ANISORATIO_4 1 +#define BRW_ANISORATIO_6 2 +#define BRW_ANISORATIO_8 3 +#define BRW_ANISORATIO_10 4 +#define BRW_ANISORATIO_12 5 +#define BRW_ANISORATIO_14 6 +#define BRW_ANISORATIO_16 7 + +#define BRW_BLENDFACTOR_ONE 0x1 +#define BRW_BLENDFACTOR_SRC_COLOR 0x2 +#define BRW_BLENDFACTOR_SRC_ALPHA 0x3 +#define BRW_BLENDFACTOR_DST_ALPHA 0x4 +#define BRW_BLENDFACTOR_DST_COLOR 0x5 +#define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 +#define BRW_BLENDFACTOR_CONST_COLOR 0x7 +#define BRW_BLENDFACTOR_CONST_ALPHA 0x8 +#define BRW_BLENDFACTOR_SRC1_COLOR 0x9 +#define BRW_BLENDFACTOR_SRC1_ALPHA 0x0A +#define BRW_BLENDFACTOR_ZERO 0x11 +#define BRW_BLENDFACTOR_INV_SRC_COLOR 0x12 +#define BRW_BLENDFACTOR_INV_SRC_ALPHA 0x13 +#define BRW_BLENDFACTOR_INV_DST_ALPHA 0x14 +#define BRW_BLENDFACTOR_INV_DST_COLOR 0x15 +#define BRW_BLENDFACTOR_INV_CONST_COLOR 0x17 +#define BRW_BLENDFACTOR_INV_CONST_ALPHA 0x18 +#define BRW_BLENDFACTOR_INV_SRC1_COLOR 0x19 +#define BRW_BLENDFACTOR_INV_SRC1_ALPHA 0x1A + +#define BRW_BLENDFUNCTION_ADD 0 +#define BRW_BLENDFUNCTION_SUBTRACT 1 +#define BRW_BLENDFUNCTION_REVERSE_SUBTRACT 2 +#define BRW_BLENDFUNCTION_MIN 3 +#define BRW_BLENDFUNCTION_MAX 4 + +#define BRW_ALPHATEST_FORMAT_UNORM8 0 +#define BRW_ALPHATEST_FORMAT_FLOAT32 1 + +#define BRW_CHROMAKEY_KILL_ON_ANY_MATCH 0 +#define BRW_CHROMAKEY_REPLACE_BLACK 1 + +#define BRW_CLIP_API_OGL 0 +#define BRW_CLIP_API_DX 1 + +#define BRW_CLIPMODE_NORMAL 0 +#define BRW_CLIPMODE_CLIP_ALL 1 +#define BRW_CLIPMODE_CLIP_NON_REJECTED 2 +#define BRW_CLIPMODE_REJECT_ALL 3 +#define BRW_CLIPMODE_ACCEPT_ALL 4 + +#define BRW_CLIP_NDCSPACE 0 +#define BRW_CLIP_SCREENSPACE 1 + +#define BRW_COMPAREFUNCTION_ALWAYS 0 +#define BRW_COMPAREFUNCTION_NEVER 1 +#define BRW_COMPAREFUNCTION_LESS 2 +#define BRW_COMPAREFUNCTION_EQUAL 3 +#define BRW_COMPAREFUNCTION_LEQUAL 4 +#define BRW_COMPAREFUNCTION_GREATER 5 +#define BRW_COMPAREFUNCTION_NOTEQUAL 6 +#define BRW_COMPAREFUNCTION_GEQUAL 7 + +#define BRW_COVERAGE_PIXELS_HALF 0 +#define BRW_COVERAGE_PIXELS_1 1 +#define BRW_COVERAGE_PIXELS_2 2 +#define BRW_COVERAGE_PIXELS_4 3 + +#define BRW_CULLMODE_BOTH 0 +#define BRW_CULLMODE_NONE 1 +#define BRW_CULLMODE_FRONT 2 +#define BRW_CULLMODE_BACK 3 + +#define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM 0 +#define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT 1 + +#define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 +#define BRW_DEPTHFORMAT_D32_FLOAT 1 +#define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2 +#define BRW_DEPTHFORMAT_D16_UNORM 5 + +#define BRW_FLOATING_POINT_IEEE_754 0 +#define BRW_FLOATING_POINT_NON_IEEE_754 1 + +#define BRW_FRONTWINDING_CW 0 +#define BRW_FRONTWINDING_CCW 1 + +#define BRW_INDEX_BYTE 0 +#define BRW_INDEX_WORD 1 +#define BRW_INDEX_DWORD 2 + +#define BRW_LOGICOPFUNCTION_CLEAR 0 +#define BRW_LOGICOPFUNCTION_NOR 1 +#define BRW_LOGICOPFUNCTION_AND_INVERTED 2 +#define BRW_LOGICOPFUNCTION_COPY_INVERTED 3 +#define BRW_LOGICOPFUNCTION_AND_REVERSE 4 +#define BRW_LOGICOPFUNCTION_INVERT 5 +#define BRW_LOGICOPFUNCTION_XOR 6 +#define BRW_LOGICOPFUNCTION_NAND 7 +#define BRW_LOGICOPFUNCTION_AND 8 +#define BRW_LOGICOPFUNCTION_EQUIV 9 +#define BRW_LOGICOPFUNCTION_NOOP 10 +#define BRW_LOGICOPFUNCTION_OR_INVERTED 11 +#define BRW_LOGICOPFUNCTION_COPY 12 +#define BRW_LOGICOPFUNCTION_OR_REVERSE 13 +#define BRW_LOGICOPFUNCTION_OR 14 +#define BRW_LOGICOPFUNCTION_SET 15 + +#define BRW_MAPFILTER_NEAREST 0x0 +#define BRW_MAPFILTER_LINEAR 0x1 +#define BRW_MAPFILTER_ANISOTROPIC 0x2 + +#define BRW_MIPFILTER_NONE 0 +#define BRW_MIPFILTER_NEAREST 1 +#define BRW_MIPFILTER_LINEAR 3 + +#define BRW_POLYGON_FRONT_FACING 0 +#define BRW_POLYGON_BACK_FACING 1 + +#define BRW_PREFILTER_ALWAYS 0x0 +#define BRW_PREFILTER_NEVER 0x1 +#define BRW_PREFILTER_LESS 0x2 +#define BRW_PREFILTER_EQUAL 0x3 +#define BRW_PREFILTER_LEQUAL 0x4 +#define BRW_PREFILTER_GREATER 0x5 +#define BRW_PREFILTER_NOTEQUAL 0x6 +#define BRW_PREFILTER_GEQUAL 0x7 + +#define BRW_PROVOKING_VERTEX_0 0 +#define BRW_PROVOKING_VERTEX_1 1 +#define BRW_PROVOKING_VERTEX_2 2 + +#define BRW_RASTRULE_UPPER_LEFT 0 +#define BRW_RASTRULE_UPPER_RIGHT 1 + +#define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0 +#define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1 +#define BRW_RENDERTARGET_CLAMPRANGE_FORMAT 2 + +#define BRW_STENCILOP_KEEP 0 +#define BRW_STENCILOP_ZERO 1 +#define BRW_STENCILOP_REPLACE 2 +#define BRW_STENCILOP_INCRSAT 3 +#define BRW_STENCILOP_DECRSAT 4 +#define BRW_STENCILOP_INCR 5 +#define BRW_STENCILOP_DECR 6 +#define BRW_STENCILOP_INVERT 7 + +#define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0 +#define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1 + +#define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 +#define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001 +#define BRW_SURFACEFORMAT_R32G32B32A32_UINT 0x002 +#define BRW_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 +#define BRW_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 +#define BRW_SURFACEFORMAT_R64G64_FLOAT 0x005 +#define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 +#define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 +#define BRW_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 +#define BRW_SURFACEFORMAT_R32G32B32_FLOAT 0x040 +#define BRW_SURFACEFORMAT_R32G32B32_SINT 0x041 +#define BRW_SURFACEFORMAT_R32G32B32_UINT 0x042 +#define BRW_SURFACEFORMAT_R32G32B32_UNORM 0x043 +#define BRW_SURFACEFORMAT_R32G32B32_SNORM 0x044 +#define BRW_SURFACEFORMAT_R32G32B32_SSCALED 0x045 +#define BRW_SURFACEFORMAT_R32G32B32_USCALED 0x046 +#define BRW_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 +#define BRW_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 +#define BRW_SURFACEFORMAT_R16G16B16A16_SINT 0x082 +#define BRW_SURFACEFORMAT_R16G16B16A16_UINT 0x083 +#define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 +#define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 +#define BRW_SURFACEFORMAT_R32G32_SINT 0x086 +#define BRW_SURFACEFORMAT_R32G32_UINT 0x087 +#define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 +#define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 +#define BRW_SURFACEFORMAT_L32A32_FLOAT 0x08A +#define BRW_SURFACEFORMAT_R32G32_UNORM 0x08B +#define BRW_SURFACEFORMAT_R32G32_SNORM 0x08C +#define BRW_SURFACEFORMAT_R64_FLOAT 0x08D +#define BRW_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E +#define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F +#define BRW_SURFACEFORMAT_A32X32_FLOAT 0x090 +#define BRW_SURFACEFORMAT_L32X32_FLOAT 0x091 +#define BRW_SURFACEFORMAT_I32X32_FLOAT 0x092 +#define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 +#define BRW_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 +#define BRW_SURFACEFORMAT_R32G32_SSCALED 0x095 +#define BRW_SURFACEFORMAT_R32G32_USCALED 0x096 +#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 +#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 +#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 +#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 +#define BRW_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 +#define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 +#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 +#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 +#define BRW_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 +#define BRW_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA +#define BRW_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB +#define BRW_SURFACEFORMAT_R16G16_UNORM 0x0CC +#define BRW_SURFACEFORMAT_R16G16_SNORM 0x0CD +#define BRW_SURFACEFORMAT_R16G16_SINT 0x0CE +#define BRW_SURFACEFORMAT_R16G16_UINT 0x0CF +#define BRW_SURFACEFORMAT_R16G16_FLOAT 0x0D0 +#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 +#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 +#define BRW_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 +#define BRW_SURFACEFORMAT_R32_SINT 0x0D6 +#define BRW_SURFACEFORMAT_R32_UINT 0x0D7 +#define BRW_SURFACEFORMAT_R32_FLOAT 0x0D8 +#define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 +#define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA +#define BRW_SURFACEFORMAT_L16A16_UNORM 0x0DF +#define BRW_SURFACEFORMAT_I24X8_UNORM 0x0E0 +#define BRW_SURFACEFORMAT_L24X8_UNORM 0x0E1 +#define BRW_SURFACEFORMAT_A24X8_UNORM 0x0E2 +#define BRW_SURFACEFORMAT_I32_FLOAT 0x0E3 +#define BRW_SURFACEFORMAT_L32_FLOAT 0x0E4 +#define BRW_SURFACEFORMAT_A32_FLOAT 0x0E5 +#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 +#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA +#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB +#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC +#define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED +#define BRW_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE +#define BRW_SURFACEFORMAT_L16A16_FLOAT 0x0F0 +#define BRW_SURFACEFORMAT_R32_UNORM 0x0F1 +#define BRW_SURFACEFORMAT_R32_SNORM 0x0F2 +#define BRW_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 +#define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 +#define BRW_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 +#define BRW_SURFACEFORMAT_R16G16_SSCALED 0x0F6 +#define BRW_SURFACEFORMAT_R16G16_USCALED 0x0F7 +#define BRW_SURFACEFORMAT_R32_SSCALED 0x0F8 +#define BRW_SURFACEFORMAT_R32_USCALED 0x0F9 +#define BRW_SURFACEFORMAT_B5G6R5_UNORM 0x100 +#define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 +#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 +#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 +#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 +#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 +#define BRW_SURFACEFORMAT_R8G8_UNORM 0x106 +#define BRW_SURFACEFORMAT_R8G8_SNORM 0x107 +#define BRW_SURFACEFORMAT_R8G8_SINT 0x108 +#define BRW_SURFACEFORMAT_R8G8_UINT 0x109 +#define BRW_SURFACEFORMAT_R16_UNORM 0x10A +#define BRW_SURFACEFORMAT_R16_SNORM 0x10B +#define BRW_SURFACEFORMAT_R16_SINT 0x10C +#define BRW_SURFACEFORMAT_R16_UINT 0x10D +#define BRW_SURFACEFORMAT_R16_FLOAT 0x10E +#define BRW_SURFACEFORMAT_I16_UNORM 0x111 +#define BRW_SURFACEFORMAT_L16_UNORM 0x112 +#define BRW_SURFACEFORMAT_A16_UNORM 0x113 +#define BRW_SURFACEFORMAT_L8A8_UNORM 0x114 +#define BRW_SURFACEFORMAT_I16_FLOAT 0x115 +#define BRW_SURFACEFORMAT_L16_FLOAT 0x116 +#define BRW_SURFACEFORMAT_A16_FLOAT 0x117 +#define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 +#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A +#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B +#define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C +#define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D +#define BRW_SURFACEFORMAT_R16_SSCALED 0x11E +#define BRW_SURFACEFORMAT_R16_USCALED 0x11F +#define BRW_SURFACEFORMAT_R8_UNORM 0x140 +#define BRW_SURFACEFORMAT_R8_SNORM 0x141 +#define BRW_SURFACEFORMAT_R8_SINT 0x142 +#define BRW_SURFACEFORMAT_R8_UINT 0x143 +#define BRW_SURFACEFORMAT_A8_UNORM 0x144 +#define BRW_SURFACEFORMAT_I8_UNORM 0x145 +#define BRW_SURFACEFORMAT_L8_UNORM 0x146 +#define BRW_SURFACEFORMAT_P4A4_UNORM 0x147 +#define BRW_SURFACEFORMAT_A4P4_UNORM 0x148 +#define BRW_SURFACEFORMAT_R8_SSCALED 0x149 +#define BRW_SURFACEFORMAT_R8_USCALED 0x14A +#define BRW_SURFACEFORMAT_R1_UINT 0x181 +#define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182 +#define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 +#define BRW_SURFACEFORMAT_BC1_UNORM 0x186 +#define BRW_SURFACEFORMAT_BC2_UNORM 0x187 +#define BRW_SURFACEFORMAT_BC3_UNORM 0x188 +#define BRW_SURFACEFORMAT_BC4_UNORM 0x189 +#define BRW_SURFACEFORMAT_BC5_UNORM 0x18A +#define BRW_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B +#define BRW_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C +#define BRW_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D +#define BRW_SURFACEFORMAT_MONO8 0x18E +#define BRW_SURFACEFORMAT_YCRCB_SWAPUV 0x18F +#define BRW_SURFACEFORMAT_YCRCB_SWAPY 0x190 +#define BRW_SURFACEFORMAT_DXT1_RGB 0x191 +#define BRW_SURFACEFORMAT_FXT1 0x192 +#define BRW_SURFACEFORMAT_R8G8B8_UNORM 0x193 +#define BRW_SURFACEFORMAT_R8G8B8_SNORM 0x194 +#define BRW_SURFACEFORMAT_R8G8B8_SSCALED 0x195 +#define BRW_SURFACEFORMAT_R8G8B8_USCALED 0x196 +#define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 +#define BRW_SURFACEFORMAT_R64G64B64_FLOAT 0x198 +#define BRW_SURFACEFORMAT_BC4_SNORM 0x199 +#define BRW_SURFACEFORMAT_BC5_SNORM 0x19A +#define BRW_SURFACEFORMAT_R16G16B16_UNORM 0x19C +#define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D +#define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E +#define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F + +#define BRW_SURFACERETURNFORMAT_FLOAT32 0 +#define BRW_SURFACERETURNFORMAT_S1 1 + +#define BRW_SURFACE_1D 0 +#define BRW_SURFACE_2D 1 +#define BRW_SURFACE_3D 2 +#define BRW_SURFACE_CUBE 3 +#define BRW_SURFACE_BUFFER 4 +#define BRW_SURFACE_NULL 7 + +#define BRW_TEXCOORDMODE_WRAP 0 +#define BRW_TEXCOORDMODE_MIRROR 1 +#define BRW_TEXCOORDMODE_CLAMP 2 +#define BRW_TEXCOORDMODE_CUBE 3 +#define BRW_TEXCOORDMODE_CLAMP_BORDER 4 +#define BRW_TEXCOORDMODE_MIRROR_ONCE 5 + +#define BRW_THREAD_PRIORITY_NORMAL 0 +#define BRW_THREAD_PRIORITY_HIGH 1 + +#define BRW_TILEWALK_XMAJOR 0 +#define BRW_TILEWALK_YMAJOR 1 + +#define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS 0 +#define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS 1 + +#define BRW_VERTEXBUFFER_ACCESS_VERTEXDATA 0 +#define BRW_VERTEXBUFFER_ACCESS_INSTANCEDATA 1 + +#define BRW_VFCOMPONENT_NOSTORE 0 +#define BRW_VFCOMPONENT_STORE_SRC 1 +#define BRW_VFCOMPONENT_STORE_0 2 +#define BRW_VFCOMPONENT_STORE_1_FLT 3 +#define BRW_VFCOMPONENT_STORE_1_INT 4 +#define BRW_VFCOMPONENT_STORE_VID 5 +#define BRW_VFCOMPONENT_STORE_IID 6 +#define BRW_VFCOMPONENT_STORE_PID 7 + + + +/* Execution Unit (EU) defines + */ + +#define BRW_ALIGN_1 0 +#define BRW_ALIGN_16 1 + +#define BRW_ADDRESS_DIRECT 0 +#define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1 + +#define BRW_CHANNEL_X 0 +#define BRW_CHANNEL_Y 1 +#define BRW_CHANNEL_Z 2 +#define BRW_CHANNEL_W 3 + +#define BRW_COMPRESSION_NONE 0 +#define BRW_COMPRESSION_2NDHALF 1 +#define BRW_COMPRESSION_COMPRESSED 2 + +#define BRW_CONDITIONAL_NONE 0 +#define BRW_CONDITIONAL_Z 1 +#define BRW_CONDITIONAL_NZ 2 +#define BRW_CONDITIONAL_EQ 1 /* Z */ +#define BRW_CONDITIONAL_NEQ 2 /* NZ */ +#define BRW_CONDITIONAL_G 3 +#define BRW_CONDITIONAL_GE 4 +#define BRW_CONDITIONAL_L 5 +#define BRW_CONDITIONAL_LE 6 +#define BRW_CONDITIONAL_C 7 +#define BRW_CONDITIONAL_O 8 + +#define BRW_DEBUG_NONE 0 +#define BRW_DEBUG_BREAKPOINT 1 + +#define BRW_DEPENDENCY_NORMAL 0 +#define BRW_DEPENDENCY_NOTCLEARED 1 +#define BRW_DEPENDENCY_NOTCHECKED 2 +#define BRW_DEPENDENCY_DISABLE 3 + +#define BRW_EXECUTE_1 0 +#define BRW_EXECUTE_2 1 +#define BRW_EXECUTE_4 2 +#define BRW_EXECUTE_8 3 +#define BRW_EXECUTE_16 4 +#define BRW_EXECUTE_32 5 + +#define BRW_HORIZONTAL_STRIDE_0 0 +#define BRW_HORIZONTAL_STRIDE_1 1 +#define BRW_HORIZONTAL_STRIDE_2 2 +#define BRW_HORIZONTAL_STRIDE_4 3 + +#define BRW_INSTRUCTION_NORMAL 0 +#define BRW_INSTRUCTION_SATURATE 1 + +#define BRW_MASK_ENABLE 0 +#define BRW_MASK_DISABLE 1 + +#define BRW_OPCODE_MOV 1 +#define BRW_OPCODE_SEL 2 +#define BRW_OPCODE_NOT 4 +#define BRW_OPCODE_AND 5 +#define BRW_OPCODE_OR 6 +#define BRW_OPCODE_XOR 7 +#define BRW_OPCODE_SHR 8 +#define BRW_OPCODE_SHL 9 +#define BRW_OPCODE_RSR 10 +#define BRW_OPCODE_RSL 11 +#define BRW_OPCODE_ASR 12 +#define BRW_OPCODE_CMP 16 +#define BRW_OPCODE_CMPN 17 +#define BRW_OPCODE_JMPI 32 +#define BRW_OPCODE_IF 34 +#define BRW_OPCODE_IFF 35 +#define BRW_OPCODE_ELSE 36 +#define BRW_OPCODE_ENDIF 37 +#define BRW_OPCODE_DO 38 +#define BRW_OPCODE_WHILE 39 +#define BRW_OPCODE_BREAK 40 +#define BRW_OPCODE_CONTINUE 41 +#define BRW_OPCODE_HALT 42 +#define BRW_OPCODE_MSAVE 44 +#define BRW_OPCODE_MRESTORE 45 +#define BRW_OPCODE_PUSH 46 +#define BRW_OPCODE_POP 47 +#define BRW_OPCODE_WAIT 48 +#define BRW_OPCODE_SEND 49 +#define BRW_OPCODE_ADD 64 +#define BRW_OPCODE_MUL 65 +#define BRW_OPCODE_AVG 66 +#define BRW_OPCODE_FRC 67 +#define BRW_OPCODE_RNDU 68 +#define BRW_OPCODE_RNDD 69 +#define BRW_OPCODE_RNDE 70 +#define BRW_OPCODE_RNDZ 71 +#define BRW_OPCODE_MAC 72 +#define BRW_OPCODE_MACH 73 +#define BRW_OPCODE_LZD 74 +#define BRW_OPCODE_SAD2 80 +#define BRW_OPCODE_SADA2 81 +#define BRW_OPCODE_DP4 84 +#define BRW_OPCODE_DPH 85 +#define BRW_OPCODE_DP3 86 +#define BRW_OPCODE_DP2 87 +#define BRW_OPCODE_DPA2 88 +#define BRW_OPCODE_LINE 89 +#define BRW_OPCODE_NOP 126 + +#define BRW_PREDICATE_NONE 0 +#define BRW_PREDICATE_NORMAL 1 +#define BRW_PREDICATE_ALIGN1_ANYV 2 +#define BRW_PREDICATE_ALIGN1_ALLV 3 +#define BRW_PREDICATE_ALIGN1_ANY2H 4 +#define BRW_PREDICATE_ALIGN1_ALL2H 5 +#define BRW_PREDICATE_ALIGN1_ANY4H 6 +#define BRW_PREDICATE_ALIGN1_ALL4H 7 +#define BRW_PREDICATE_ALIGN1_ANY8H 8 +#define BRW_PREDICATE_ALIGN1_ALL8H 9 +#define BRW_PREDICATE_ALIGN1_ANY16H 10 +#define BRW_PREDICATE_ALIGN1_ALL16H 11 +#define BRW_PREDICATE_ALIGN16_REPLICATE_X 2 +#define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3 +#define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4 +#define BRW_PREDICATE_ALIGN16_REPLICATE_W 5 +#define BRW_PREDICATE_ALIGN16_ANY4H 6 +#define BRW_PREDICATE_ALIGN16_ALL4H 7 + +#define BRW_ARCHITECTURE_REGISTER_FILE 0 +#define BRW_GENERAL_REGISTER_FILE 1 +#define BRW_MESSAGE_REGISTER_FILE 2 +#define BRW_IMMEDIATE_VALUE 3 + +#define BRW_REGISTER_TYPE_UD 0 +#define BRW_REGISTER_TYPE_D 1 +#define BRW_REGISTER_TYPE_UW 2 +#define BRW_REGISTER_TYPE_W 3 +#define BRW_REGISTER_TYPE_UB 4 +#define BRW_REGISTER_TYPE_B 5 +#define BRW_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */ +#define BRW_REGISTER_TYPE_HF 6 +#define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */ +#define BRW_REGISTER_TYPE_F 7 + +#define BRW_ARF_NULL 0x00 +#define BRW_ARF_ADDRESS 0x10 +#define BRW_ARF_ACCUMULATOR 0x20 +#define BRW_ARF_FLAG 0x30 +#define BRW_ARF_MASK 0x40 +#define BRW_ARF_MASK_STACK 0x50 +#define BRW_ARF_MASK_STACK_DEPTH 0x60 +#define BRW_ARF_STATE 0x70 +#define BRW_ARF_CONTROL 0x80 +#define BRW_ARF_NOTIFICATION_COUNT 0x90 +#define BRW_ARF_IP 0xA0 + +#define BRW_AMASK 0 +#define BRW_IMASK 1 +#define BRW_LMASK 2 +#define BRW_CMASK 3 + + + +#define BRW_THREAD_NORMAL 0 +#define BRW_THREAD_ATOMIC 1 +#define BRW_THREAD_SWITCH 2 + +#define BRW_VERTICAL_STRIDE_0 0 +#define BRW_VERTICAL_STRIDE_1 1 +#define BRW_VERTICAL_STRIDE_2 2 +#define BRW_VERTICAL_STRIDE_4 3 +#define BRW_VERTICAL_STRIDE_8 4 +#define BRW_VERTICAL_STRIDE_16 5 +#define BRW_VERTICAL_STRIDE_32 6 +#define BRW_VERTICAL_STRIDE_64 7 +#define BRW_VERTICAL_STRIDE_128 8 +#define BRW_VERTICAL_STRIDE_256 9 +#define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF + +#define BRW_WIDTH_1 0 +#define BRW_WIDTH_2 1 +#define BRW_WIDTH_4 2 +#define BRW_WIDTH_8 3 +#define BRW_WIDTH_16 4 + +#define BRW_STATELESS_BUFFER_BOUNDARY_1K 0 +#define BRW_STATELESS_BUFFER_BOUNDARY_2K 1 +#define BRW_STATELESS_BUFFER_BOUNDARY_4K 2 +#define BRW_STATELESS_BUFFER_BOUNDARY_8K 3 +#define BRW_STATELESS_BUFFER_BOUNDARY_16K 4 +#define BRW_STATELESS_BUFFER_BOUNDARY_32K 5 +#define BRW_STATELESS_BUFFER_BOUNDARY_64K 6 +#define BRW_STATELESS_BUFFER_BOUNDARY_128K 7 +#define BRW_STATELESS_BUFFER_BOUNDARY_256K 8 +#define BRW_STATELESS_BUFFER_BOUNDARY_512K 9 +#define BRW_STATELESS_BUFFER_BOUNDARY_1M 10 +#define BRW_STATELESS_BUFFER_BOUNDARY_2M 11 + +#define BRW_POLYGON_FACING_FRONT 0 +#define BRW_POLYGON_FACING_BACK 1 + +#define BRW_MESSAGE_TARGET_NULL 0 +#define BRW_MESSAGE_TARGET_MATH 1 +#define BRW_MESSAGE_TARGET_SAMPLER 2 +#define BRW_MESSAGE_TARGET_GATEWAY 3 +#define BRW_MESSAGE_TARGET_DATAPORT_READ 4 +#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5 +#define BRW_MESSAGE_TARGET_URB 6 +#define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7 + +#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0 +#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2 +#define BRW_SAMPLER_RETURN_FORMAT_SINT32 3 + +#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 +#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 +#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 +#define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 +#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 +#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 +#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 +#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 +#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 +#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 +#define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 +#define BRW_SAMPLER_MESSAGE_SIMD8_RESINFO 2 +#define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2 +#define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3 +#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 +#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 + +#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 +#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 +#define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2 +#define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3 +#define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4 + +#define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 +#define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 + +#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 +#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 + +#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 +#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 +#define BRW_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2 +#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 + +#define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0 +#define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1 +#define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 + +#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 +#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 +#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 +#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 +#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 + +#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 +#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 +#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2 +#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 +#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 +#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 +#define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 + +#define BRW_MATH_FUNCTION_INV 1 +#define BRW_MATH_FUNCTION_LOG 2 +#define BRW_MATH_FUNCTION_EXP 3 +#define BRW_MATH_FUNCTION_SQRT 4 +#define BRW_MATH_FUNCTION_RSQ 5 +#define BRW_MATH_FUNCTION_SIN 6 /* was 7 */ +#define BRW_MATH_FUNCTION_COS 7 /* was 8 */ +#define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */ +#define BRW_MATH_FUNCTION_TAN 9 +#define BRW_MATH_FUNCTION_POW 10 +#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 +#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12 +#define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13 + +#define BRW_MATH_INTEGER_UNSIGNED 0 +#define BRW_MATH_INTEGER_SIGNED 1 + +#define BRW_MATH_PRECISION_FULL 0 +#define BRW_MATH_PRECISION_PARTIAL 1 + +#define BRW_MATH_SATURATE_NONE 0 +#define BRW_MATH_SATURATE_SATURATE 1 + +#define BRW_MATH_DATA_VECTOR 0 +#define BRW_MATH_DATA_SCALAR 1 + +#define BRW_URB_OPCODE_WRITE 0 + +#define BRW_URB_SWIZZLE_NONE 0 +#define BRW_URB_SWIZZLE_INTERLEAVE 1 +#define BRW_URB_SWIZZLE_TRANSPOSE 2 + +#define BRW_SCRATCH_SPACE_SIZE_1K 0 +#define BRW_SCRATCH_SPACE_SIZE_2K 1 +#define BRW_SCRATCH_SPACE_SIZE_4K 2 +#define BRW_SCRATCH_SPACE_SIZE_8K 3 +#define BRW_SCRATCH_SPACE_SIZE_16K 4 +#define BRW_SCRATCH_SPACE_SIZE_32K 5 +#define BRW_SCRATCH_SPACE_SIZE_64K 6 +#define BRW_SCRATCH_SPACE_SIZE_128K 7 +#define BRW_SCRATCH_SPACE_SIZE_256K 8 +#define BRW_SCRATCH_SPACE_SIZE_512K 9 +#define BRW_SCRATCH_SPACE_SIZE_1M 10 +#define BRW_SCRATCH_SPACE_SIZE_2M 11 + + + + +#define CMD_URB_FENCE 0x6000 +#define CMD_CONST_BUFFER_STATE 0x6001 +#define CMD_CONST_BUFFER 0x6002 + +#define CMD_STATE_BASE_ADDRESS 0x6101 +#define CMD_STATE_INSN_POINTER 0x6102 +#define CMD_PIPELINE_SELECT 0x6104 + +#define CMD_PIPELINED_STATE_POINTERS 0x7800 +#define CMD_BINDING_TABLE_PTRS 0x7801 +#define CMD_VERTEX_BUFFER 0x7808 +#define CMD_VERTEX_ELEMENT 0x7809 +#define CMD_INDEX_BUFFER 0x780a +#define CMD_VF_STATISTICS 0x780b + +#define CMD_DRAW_RECT 0x7900 +#define CMD_BLEND_CONSTANT_COLOR 0x7901 +#define CMD_CHROMA_KEY 0x7904 +#define CMD_DEPTH_BUFFER 0x7905 +#define CMD_POLY_STIPPLE_OFFSET 0x7906 +#define CMD_POLY_STIPPLE_PATTERN 0x7907 +#define CMD_LINE_STIPPLE_PATTERN 0x7908 +#define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7908 + +#define CMD_PIPE_CONTROL 0x7a00 + +#define CMD_3D_PRIM 0x7b00 + +#define CMD_MI_FLUSH 0x0200 + + +/* Various values from the R0 vertex header: + */ +#define R02_PRIM_END 0x1 +#define R02_PRIM_START 0x2 + + + +#endif diff --git a/assembler/src/brw_structs.h b/assembler/src/brw_structs.h new file mode 100644 index 00000000..a5acbe3d --- /dev/null +++ b/assembler/src/brw_structs.h @@ -0,0 +1,1327 @@ + /************************************************************************** + * + * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#ifndef BRW_STRUCTS_H +#define BRW_STRUCTS_H + +/* Command packets: + */ +struct header +{ + GLuint length:16; + GLuint opcode:16; +} bits; + + +union header_union +{ + struct header bits; + GLuint dword; +}; + +struct brw_3d_control +{ + struct + { + GLuint length:8; + GLuint notify_enable:1; + GLuint pad:3; + GLuint wc_flush_enable:1; + GLuint depth_stall_enable:1; + GLuint operation:2; + GLuint opcode:16; + } header; + + struct + { + GLuint pad:2; + GLuint dest_addr_type:1; + GLuint dest_addr:29; + } dest; + + GLuint dword2; + GLuint dword3; +}; + + +struct brw_3d_primitive +{ + struct + { + GLuint length:8; + GLuint pad:2; + GLuint topology:5; + GLuint indexed:1; + GLuint opcode:16; + } header; + + GLuint verts_per_instance; + GLuint start_vert_location; + GLuint instance_count; + GLuint start_instance_location; + GLuint base_vert_location; +}; + +/* These seem to be passed around as function args, so it works out + * better to keep them as #defines: + */ +#define BRW_FLUSH_READ_CACHE 0x1 +#define BRW_FLUSH_STATE_CACHE 0x2 +#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4 +#define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8 + +struct brw_mi_flush +{ + GLuint flags:4; + GLuint pad:12; + GLuint opcode:16; +}; + +struct brw_vf_statistics +{ + GLuint statistics_enable:1; + GLuint pad:15; + GLuint opcode:16; +}; + + + +struct brw_binding_table_pointers +{ + struct header header; + GLuint vs; + GLuint gs; + GLuint clp; + GLuint sf; + GLuint wm; +}; + + +struct brw_blend_constant_color +{ + struct header header; + GLfloat blend_constant_color[4]; +}; + + +struct brw_depthbuffer +{ + union header_union header; + + union { + struct { + GLuint pitch:18; + GLuint format:3; + GLuint pad:4; + GLuint depth_offset_disable:1; + GLuint tile_walk:1; + GLuint tiled_surface:1; + GLuint pad2:1; + GLuint surface_type:3; + } bits; + GLuint dword; + } dword1; + + GLuint dword2_base_addr; + + union { + struct { + GLuint pad:1; + GLuint mipmap_layout:1; + GLuint lod:4; + GLuint width:13; + GLuint height:13; + } bits; + GLuint dword; + } dword3; + + union { + struct { + GLuint pad:12; + GLuint min_array_element:9; + GLuint depth:11; + } bits; + GLuint dword; + } dword4; +}; + +struct brw_drawrect +{ + struct header header; + GLuint xmin:16; + GLuint ymin:16; + GLuint xmax:16; + GLuint ymax:16; + GLuint xorg:16; + GLuint yorg:16; +}; + + + + +struct brw_global_depth_offset_clamp +{ + struct header header; + GLfloat depth_offset_clamp; +}; + +struct brw_indexbuffer +{ + union { + struct + { + GLuint length:8; + GLuint index_format:2; + GLuint cut_index_enable:1; + GLuint pad:5; + GLuint opcode:16; + } bits; + GLuint dword; + + } header; + + GLuint buffer_start; + GLuint buffer_end; +}; + + +struct brw_line_stipple +{ + struct header header; + + struct + { + GLuint pattern:16; + GLuint pad:16; + } bits0; + + struct + { + GLuint repeat_count:9; + GLuint pad:7; + GLuint inverse_repeat_count:16; + } bits1; +}; + + +struct brw_pipelined_state_pointers +{ + struct header header; + + struct { + GLuint pad:5; + GLuint offset:27; + } vs; + + struct + { + GLuint enable:1; + GLuint pad:4; + GLuint offset:27; + } gs; + + struct + { + GLuint enable:1; + GLuint pad:4; + GLuint offset:27; + } clp; + + struct + { + GLuint pad:5; + GLuint offset:27; + } sf; + + struct + { + GLuint pad:5; + GLuint offset:27; + } wm; + + struct + { + GLuint pad:5; + GLuint offset:27; /* KW: check me! */ + } cc; +}; + + +struct brw_polygon_stipple_offset +{ + struct header header; + + struct { + GLuint y_offset:5; + GLuint pad:3; + GLuint x_offset:5; + GLuint pad0:19; + } bits0; +}; + + + +struct brw_polygon_stipple +{ + struct header header; + GLuint stipple[32]; +}; + + + +struct brw_pipeline_select +{ + struct + { + GLuint pipeline_select:1; + GLuint pad:15; + GLuint opcode:16; + } header; +}; + + +struct brw_pipe_control +{ + struct + { + GLuint length:8; + GLuint notify_enable:1; + GLuint pad:2; + GLuint instruction_state_cache_flush_enable:1; + GLuint write_cache_flush_enable:1; + GLuint depth_stall_enable:1; + GLuint post_sync_operation:2; + + GLuint opcode:16; + } header; + + struct + { + GLuint pad:2; + GLuint dest_addr_type:1; + GLuint dest_addr:29; + } bits1; + + GLuint data0; + GLuint data1; +}; + + +struct brw_urb_fence +{ + struct + { + GLuint length:8; + GLuint vs_realloc:1; + GLuint gs_realloc:1; + GLuint clp_realloc:1; + GLuint sf_realloc:1; + GLuint vfe_realloc:1; + GLuint cs_realloc:1; + GLuint pad:2; + GLuint opcode:16; + } header; + + struct + { + GLuint vs_fence:10; + GLuint gs_fence:10; + GLuint clp_fence:10; + GLuint pad:2; + } bits0; + + struct + { + GLuint sf_fence:10; + GLuint vf_fence:10; + GLuint cs_fence:10; + GLuint pad:2; + } bits1; +}; + +struct brw_constant_buffer_state /* previously brw_command_streamer */ +{ + struct header header; + + struct + { + GLuint nr_urb_entries:3; + GLuint pad:1; + GLuint urb_entry_size:5; + GLuint pad0:23; + } bits0; +}; + +struct brw_constant_buffer +{ + struct + { + GLuint length:8; + GLuint valid:1; + GLuint pad:7; + GLuint opcode:16; + } header; + + struct + { + GLuint buffer_length:6; + GLuint buffer_address:26; + } bits0; +}; + +struct brw_state_base_address +{ + struct header header; + + struct + { + GLuint modify_enable:1; + GLuint pad:4; + GLuint general_state_address:27; + } bits0; + + struct + { + GLuint modify_enable:1; + GLuint pad:4; + GLuint surface_state_address:27; + } bits1; + + struct + { + GLuint modify_enable:1; + GLuint pad:4; + GLuint indirect_object_state_address:27; + } bits2; + + struct + { + GLuint modify_enable:1; + GLuint pad:11; + GLuint general_state_upper_bound:20; + } bits3; + + struct + { + GLuint modify_enable:1; + GLuint pad:11; + GLuint indirect_object_state_upper_bound:20; + } bits4; +}; + +struct brw_state_prefetch +{ + struct header header; + + struct + { + GLuint prefetch_count:3; + GLuint pad:3; + GLuint prefetch_pointer:26; + } bits0; +}; + +struct brw_system_instruction_pointer +{ + struct header header; + + struct + { + GLuint pad:4; + GLuint system_instruction_pointer:28; + } bits0; +}; + + + + +/* State structs for the various fixed function units: + */ + + +struct thread0 +{ + GLuint pad0:1; + GLuint grf_reg_count:3; + GLuint pad1:2; + GLuint kernel_start_pointer:26; +}; + +struct thread1 +{ + GLuint ext_halt_exception_enable:1; + GLuint sw_exception_enable:1; + GLuint mask_stack_exception_enable:1; + GLuint timeout_exception_enable:1; + GLuint illegal_op_exception_enable:1; + GLuint pad0:3; + GLuint depth_coef_urb_read_offset:6; /* WM only */ + GLuint pad1:2; + GLuint floating_point_mode:1; + GLuint thread_priority:1; + GLuint binding_table_entry_count:8; + GLuint pad3:5; + GLuint single_program_flow:1; +}; + +struct thread2 +{ + GLuint per_thread_scratch_space:4; + GLuint pad0:6; + GLuint scratch_space_base_pointer:22; +}; + + +struct thread3 +{ + GLuint dispatch_grf_start_reg:4; + GLuint urb_entry_read_offset:6; + GLuint pad0:1; + GLuint urb_entry_read_length:6; + GLuint pad1:1; + GLuint const_urb_entry_read_offset:6; + GLuint pad2:1; + GLuint const_urb_entry_read_length:6; + GLuint pad3:1; +}; + + + +struct brw_clip_unit_state +{ + struct thread0 thread0; + struct thread1 thread1; + struct thread2 thread2; + struct thread3 thread3; + + struct + { + GLuint pad0:9; + GLuint gs_output_stats:1; /* not always */ + GLuint stats_enable:1; + GLuint nr_urb_entries:7; + GLuint pad1:1; + GLuint urb_entry_allocation_size:5; + GLuint pad2:1; + GLuint max_threads:6; /* may be less */ + GLuint pad3:1; + } thread4; + + struct + { + GLuint pad0:13; + GLuint clip_mode:3; + GLuint userclip_enable_flags:8; + GLuint userclip_must_clip:1; + GLuint pad1:1; + GLuint guard_band_enable:1; + GLuint viewport_z_clip_enable:1; + GLuint viewport_xy_clip_enable:1; + GLuint vertex_position_space:1; + GLuint api_mode:1; + GLuint pad2:1; + } clip5; + + struct + { + GLuint pad0:5; + GLuint clipper_viewport_state_ptr:27; + } clip6; + + + GLfloat viewport_xmin; + GLfloat viewport_xmax; + GLfloat viewport_ymin; + GLfloat viewport_ymax; +}; + + + +struct brw_cc_unit_state +{ + struct + { + GLuint pad0:3; + GLuint bf_stencil_pass_depth_pass_op:3; + GLuint bf_stencil_pass_depth_fail_op:3; + GLuint bf_stencil_fail_op:3; + GLuint bf_stencil_func:3; + GLuint bf_stencil_enable:1; + GLuint pad1:2; + GLuint stencil_write_enable:1; + GLuint stencil_pass_depth_pass_op:3; + GLuint stencil_pass_depth_fail_op:3; + GLuint stencil_fail_op:3; + GLuint stencil_func:3; + GLuint stencil_enable:1; + } cc0; + + + struct + { + GLuint bf_stencil_ref:8; + GLuint stencil_write_mask:8; + GLuint stencil_test_mask:8; + GLuint stencil_ref:8; + } cc1; + + + struct + { + GLuint logicop_enable:1; + GLuint pad0:10; + GLuint depth_write_enable:1; + GLuint depth_test_function:3; + GLuint depth_test:1; + GLuint bf_stencil_write_mask:8; + GLuint bf_stencil_test_mask:8; + } cc2; + + + struct + { + GLuint pad0:8; + GLuint alpha_test_func:3; + GLuint alpha_test:1; + GLuint blend_enable:1; + GLuint ia_blend_enable:1; + GLuint pad1:1; + GLuint alpha_test_format:1; + GLuint pad2:16; + } cc3; + + struct + { + GLuint pad0:5; + GLuint cc_viewport_state_offset:27; + } cc4; + + struct + { + GLuint pad0:2; + GLuint ia_dest_blend_factor:5; + GLuint ia_src_blend_factor:5; + GLuint ia_blend_function:3; + GLuint statistics_enable:1; + GLuint logicop_func:4; + GLuint pad1:11; + GLuint dither_enable:1; + } cc5; + + struct + { + GLuint clamp_post_alpha_blend:1; + GLuint clamp_pre_alpha_blend:1; + GLuint clamp_range:2; + GLuint pad0:11; + GLuint y_dither_offset:2; + GLuint x_dither_offset:2; + GLuint dest_blend_factor:5; + GLuint src_blend_factor:5; + GLuint blend_function:3; + } cc6; + + struct { + union { + GLfloat f; + GLubyte ub[4]; + } alpha_ref; + } cc7; +}; + + + +struct brw_sf_unit_state +{ + struct thread0 thread0; + struct thread1 thread1; + struct thread2 thread2; + struct thread3 thread3; + + struct + { + GLuint pad0:10; + GLuint stats_enable:1; + GLuint nr_urb_entries:7; + GLuint pad1:1; + GLuint urb_entry_allocation_size:5; + GLuint pad2:1; + GLuint max_threads:6; + GLuint pad3:1; + } thread4; + + struct + { + GLuint front_winding:1; + GLuint viewport_transform:1; + GLuint pad0:3; + GLuint sf_viewport_state_offset:27; + } sf5; + + struct + { + GLuint pad0:9; + GLuint dest_org_vbias:4; + GLuint dest_org_hbias:4; + GLuint scissor:1; + GLuint disable_2x2_trifilter:1; + GLuint disable_zero_pix_trifilter:1; + GLuint point_rast_rule:2; + GLuint line_endcap_aa_region_width:2; + GLuint line_width:4; + GLuint fast_scissor_disable:1; + GLuint cull_mode:2; + GLuint aa_enable:1; + } sf6; + + struct + { + GLuint point_size:11; + GLuint use_point_size_state:1; + GLuint subpixel_precision:1; + GLuint sprite_point:1; + GLuint pad0:11; + GLuint trifan_pv:2; + GLuint linestrip_pv:2; + GLuint tristrip_pv:2; + GLuint line_last_pixel_enable:1; + } sf7; + +}; + + +struct brw_gs_unit_state +{ + struct thread0 thread0; + struct thread1 thread1; + struct thread2 thread2; + struct thread3 thread3; + + struct + { + GLuint pad0:10; + GLuint stats_enable:1; + GLuint nr_urb_entries:7; + GLuint pad1:1; + GLuint urb_entry_allocation_size:5; + GLuint pad2:1; + GLuint max_threads:1; + GLuint pad3:6; + } thread4; + + struct + { + GLuint sampler_count:3; + GLuint pad0:2; + GLuint sampler_state_pointer:27; + } gs5; + + + struct + { + GLuint max_vp_index:4; + GLuint pad0:26; + GLuint reorder_enable:1; + GLuint pad1:1; + } gs6; +}; + + +struct brw_vs_unit_state +{ + struct thread0 thread0; + struct thread1 thread1; + struct thread2 thread2; + struct thread3 thread3; + + struct + { + GLuint pad0:10; + GLuint stats_enable:1; + GLuint nr_urb_entries:7; + GLuint pad1:1; + GLuint urb_entry_allocation_size:5; + GLuint pad2:1; + GLuint max_threads:4; + GLuint pad3:3; + } thread4; + + struct + { + GLuint sampler_count:3; + GLuint pad0:2; + GLuint sampler_state_pointer:27; + } vs5; + + struct + { + GLuint vs_enable:1; + GLuint vert_cache_disable:1; + GLuint pad0:30; + } vs6; +}; + + +struct brw_wm_unit_state +{ + struct thread0 thread0; + struct thread1 thread1; + struct thread2 thread2; + struct thread3 thread3; + + struct { + GLuint stats_enable:1; + GLuint pad0:1; + GLuint sampler_count:3; + GLuint sampler_state_pointer:27; + } wm4; + + struct + { + GLuint enable_8_pix:1; + GLuint enable_16_pix:1; + GLuint enable_32_pix:1; + GLuint pad0:7; + GLuint legacy_global_depth_bias:1; + GLuint line_stipple:1; + GLuint depth_offset:1; + GLuint polygon_stipple:1; + GLuint line_aa_region_width:2; + GLuint line_endcap_aa_region_width:2; + GLuint early_depth_test:1; + GLuint thread_dispatch_enable:1; + GLuint program_uses_depth:1; + GLuint program_computes_depth:1; + GLuint program_uses_killpixel:1; + GLuint legacy_line_rast: 1; + GLuint pad1:1; + GLuint max_threads:6; + GLuint pad2:1; + } wm5; + + GLfloat global_depth_offset_constant; + GLfloat global_depth_offset_scale; +}; + +struct brw_sampler_default_color { + GLfloat color[4]; +}; + +struct brw_sampler_state +{ + + struct + { + GLuint shadow_function:3; + GLuint lod_bias:11; + GLuint min_filter:3; + GLuint mag_filter:3; + GLuint mip_filter:2; + GLuint base_level:5; + GLuint pad:1; + GLuint lod_preclamp:1; + GLuint default_color_mode:1; + GLuint pad0:1; + GLuint disable:1; + } ss0; + + struct + { + GLuint r_wrap_mode:3; + GLuint t_wrap_mode:3; + GLuint s_wrap_mode:3; + GLuint pad:3; + GLuint max_lod:10; + GLuint min_lod:10; + } ss1; + + + struct + { + GLuint pad:5; + GLuint default_color_pointer:27; + } ss2; + + struct + { + GLuint pad:19; + GLuint max_aniso:3; + GLuint chroma_key_mode:1; + GLuint chroma_key_index:2; + GLuint chroma_key_enable:1; + GLuint monochrome_filter_width:3; + GLuint monochrome_filter_height:3; + } ss3; +}; + + +struct brw_clipper_viewport +{ + GLfloat xmin; + GLfloat xmax; + GLfloat ymin; + GLfloat ymax; +}; + +struct brw_cc_viewport +{ + GLfloat min_depth; + GLfloat max_depth; +}; + +struct brw_sf_viewport +{ + struct { + GLfloat m00; + GLfloat m11; + GLfloat m22; + GLfloat m30; + GLfloat m31; + GLfloat m32; + } viewport; + + struct { + GLshort xmin; + GLshort ymin; + GLshort xmax; + GLshort ymax; + } scissor; +}; + +/* Documented in the subsystem/shared-functions/sampler chapter... + */ +struct brw_surface_state +{ + struct { + GLuint cube_pos_z:1; + GLuint cube_neg_z:1; + GLuint cube_pos_y:1; + GLuint cube_neg_y:1; + GLuint cube_pos_x:1; + GLuint cube_neg_x:1; + GLuint pad:4; + GLuint mipmap_layout_mode:1; + GLuint vert_line_stride_ofs:1; + GLuint vert_line_stride:1; + GLuint color_blend:1; + GLuint writedisable_blue:1; + GLuint writedisable_green:1; + GLuint writedisable_red:1; + GLuint writedisable_alpha:1; + GLuint surface_format:9; + GLuint data_return_format:1; + GLuint pad0:1; + GLuint surface_type:3; + } ss0; + + struct { + GLuint base_addr; + } ss1; + + struct { + GLuint pad:2; + GLuint mip_count:4; + GLuint width:13; + GLuint height:13; + } ss2; + + struct { + GLuint tile_walk:1; + GLuint tiled_surface:1; + GLuint pad:1; + GLuint pitch:18; + GLuint depth:11; + } ss3; + + struct { + GLuint pad:19; + GLuint min_array_elt:9; + GLuint min_lod:4; + } ss4; +}; + + + +struct brw_vertex_buffer_state +{ + struct { + GLuint pitch:11; + GLuint pad:15; + GLuint access_type:1; + GLuint vb_index:5; + } vb0; + + GLuint start_addr; + GLuint max_index; +#if 1 + GLuint instance_data_step_rate; /* not included for sequential/random vertices? */ +#endif +}; + +#define BRW_VBP_MAX 17 + +struct brw_vb_array_state { + struct header header; + struct brw_vertex_buffer_state vb[BRW_VBP_MAX]; +}; + + +struct brw_vertex_element_state +{ + struct + { + GLuint src_offset:11; + GLuint pad:5; + GLuint src_format:9; + GLuint pad0:1; + GLuint valid:1; + GLuint vertex_buffer_index:5; + } ve0; + + struct + { + GLuint dst_offset:8; + GLuint pad:8; + GLuint vfcomponent3:4; + GLuint vfcomponent2:4; + GLuint vfcomponent1:4; + GLuint vfcomponent0:4; + } ve1; +}; + +#define BRW_VEP_MAX 18 + +struct brw_vertex_element_packet { + struct header header; + struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */ +}; + + +struct brw_urb_immediate { + GLuint opcode:4; + GLuint offset:6; + GLuint swizzle_control:2; + GLuint pad:1; + GLuint allocate:1; + GLuint used:1; + GLuint complete:1; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; +}; + +/* Instruction format for the execution units: + */ + +struct brw_instruction +{ + struct + { + GLuint opcode:7; + GLuint pad:1; + GLuint access_mode:1; + GLuint mask_control:1; + GLuint dependency_control:2; + GLuint compression_control:2; + GLuint thread_control:2; + GLuint predicate_control:4; + GLuint predicate_inverse:1; + GLuint execution_size:3; + GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */ + GLuint pad0:2; + GLuint debug_control:1; + GLuint saturate:1; + } header; + + union { + struct + { + GLuint dest_reg_file:2; + GLuint dest_reg_type:3; + GLuint src0_reg_file:2; + GLuint src0_reg_type:3; + GLuint src1_reg_file:2; + GLuint src1_reg_type:3; + GLuint pad:1; + GLuint dest_subreg_nr:5; + GLuint dest_reg_nr:8; + GLuint dest_horiz_stride:2; + GLuint dest_address_mode:1; + } da1; + + struct + { + GLuint dest_reg_file:2; + GLuint dest_reg_type:3; + GLuint src0_reg_file:2; + GLuint src0_reg_type:3; + GLuint pad:6; + GLint dest_indirect_offset:10; /* offset against the deref'd address reg */ + GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */ + GLuint dest_horiz_stride:2; + GLuint dest_address_mode:1; + } ia1; + + struct + { + GLuint dest_reg_file:2; + GLuint dest_reg_type:3; + GLuint src0_reg_file:2; + GLuint src0_reg_type:3; + GLuint src1_reg_file:2; + GLuint src1_reg_type:3; + GLuint pad0:1; + GLuint dest_writemask:4; + GLuint dest_subreg_nr:1; + GLuint dest_reg_nr:8; + GLuint pad1:2; + GLuint dest_address_mode:1; + } da16; + + struct + { + GLuint dest_reg_file:2; + GLuint dest_reg_type:3; + GLuint src0_reg_file:2; + GLuint src0_reg_type:3; + GLuint pad0:6; + GLuint dest_writemask:4; + GLint dest_indirect_offset:6; + GLuint dest_subreg_nr:3; + GLuint pad1:2; + GLuint dest_address_mode:1; + } ia16; + } bits1; + + + union { + struct + { + GLuint src0_subreg_nr:5; + GLuint src0_reg_nr:8; + GLuint src0_abs:1; + GLuint src0_negate:1; + GLuint src0_address_mode:1; + GLuint src0_horiz_stride:2; + GLuint src0_width:3; + GLuint src0_vert_stride:4; + GLuint flag_reg_nr:1; + GLuint pad:6; + } da1; + + struct + { + GLint src0_indirect_offset:10; + GLuint src0_subreg_nr:3; + GLuint src0_abs:1; + GLuint src0_negate:1; + GLuint src0_address_mode:1; + GLuint src0_horiz_stride:2; + GLuint src0_width:3; + GLuint src0_vert_stride:4; + GLuint flag_reg_nr:1; + GLuint pad:6; + } ia1; + + struct + { + GLuint src0_swz_x:2; + GLuint src0_swz_y:2; + GLuint src0_subreg_nr:1; + GLuint src0_reg_nr:8; + GLuint src0_abs:1; + GLuint src0_negate:1; + GLuint src0_address_mode:1; + GLuint src0_swz_z:2; + GLuint src0_swz_w:2; + GLuint pad0:1; + GLuint src0_vert_stride:4; + GLuint flag_reg_nr:1; + GLuint pad1:6; + } da16; + + struct + { + GLuint src0_swz_x:2; + GLuint src0_swz_y:2; + GLint src0_indirect_offset:6; + GLuint src0_subreg_nr:3; + GLuint src0_abs:1; + GLuint src0_negate:1; + GLuint src0_address_mode:1; + GLuint src0_swz_z:2; + GLuint src0_swz_w:2; + GLuint pad0:1; + GLuint src0_vert_stride:4; + GLuint flag_reg_nr:1; + GLuint pad1:6; + } ia16; + + } bits2; + + union + { + struct + { + GLuint src1_subreg_nr:5; + GLuint src1_reg_nr:8; + GLuint src1_abs:1; + GLuint src1_negate:1; + GLuint pad:1; + GLuint src1_horiz_stride:2; + GLuint src1_width:3; + GLuint src1_vert_stride:4; + GLuint pad0:7; + } da1; + + struct + { + GLuint src1_swz_x:2; + GLuint src1_swz_y:2; + GLuint src1_subreg_nr:1; + GLuint src1_reg_nr:8; + GLuint src1_abs:1; + GLuint src1_negate:1; + GLuint pad0:1; + GLuint src1_swz_z:2; + GLuint src1_swz_w:2; + GLuint pad1:1; + GLuint src1_vert_stride:4; + GLuint pad2:7; + } da16; + + struct + { + GLint src1_indirect_offset:10; + GLuint src1_subreg_nr:3; + GLuint src1_abs:1; + GLuint src1_negate:1; + GLuint pad0:1; + GLuint src1_horiz_stride:2; + GLuint src1_width:3; + GLuint src1_vert_stride:4; + GLuint flag_reg_nr:1; + GLuint pad1:6; + } ia1; + + struct + { + GLuint src1_swz_x:2; + GLuint src1_swz_y:2; + GLint src1_indirect_offset:6; + GLuint src1_subreg_nr:3; + GLuint src1_abs:1; + GLuint src1_negate:1; + GLuint pad0:1; + GLuint src1_swz_z:2; + GLuint src1_swz_w:2; + GLuint pad1:1; + GLuint src1_vert_stride:4; + GLuint flag_reg_nr:1; + GLuint pad2:6; + } ia16; + + + struct + { + GLint jump_count:16; /* note: signed */ + GLuint pop_count:4; + GLuint pad0:12; + } if_else; + + struct { + GLuint function:4; + GLuint int_type:1; + GLuint precision:1; + GLuint saturate:1; + GLuint data_type:1; + GLuint pad0:8; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; + } math; + + struct { + GLuint binding_table_index:8; + GLuint sampler:4; + GLuint return_format:2; + GLuint msg_type:2; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; + } sampler; + + struct brw_urb_immediate urb; + + struct { + GLuint binding_table_index:8; + GLuint msg_control:4; + GLuint msg_type:2; + GLuint target_cache:2; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; + } dp_read; + + struct { + GLuint binding_table_index:8; + GLuint msg_control:3; + GLuint pixel_scoreboard_clear:1; + GLuint msg_type:3; + GLuint send_commit_msg:1; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; + } dp_write; + + struct { + GLuint pad:16; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; + } generic; + + GLuint ud; + GLint id; + GLfloat fd; + } bits3; +}; + + +#endif diff --git a/assembler/src/gen4asm.h b/assembler/src/gen4asm.h new file mode 100644 index 00000000..2db36994 --- /dev/null +++ b/assembler/src/gen4asm.h @@ -0,0 +1,103 @@ +/* -*- c-basic-offset: 8 -*- */ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Eric Anholt <eric@anholt.net> + * + */ + +#include <sys/types.h> + +typedef unsigned char GLubyte; +typedef short GLshort; +typedef unsigned int GLuint; +typedef int GLint; +typedef float GLfloat; + +#include "brw_structs.h" + +void yyerror (char *msg); + +/** + * This structure is the internal representation of destination operands in the + * parser. + */ +struct dst_operand { + int reg_file, reg_nr, subreg_nr, reg_type; + + int writemask_set; + int writemask; + + int horiz_stride; + int address_mode; /* 0 if direct, 1 if register-indirect */ + + /* Indirect addressing */ + int address_subreg_nr; + int indirect_offset; +}; + +/** + * This structure is the internal representation of source operands in the + * parser. + */ +struct src_operand { + int reg_file, reg_nr, subreg_nr, reg_type; + + int abs, negate; + + int horiz_stride, width, vert_stride; + + int address_mode; /* 0 if direct, 1 if register-indirect */ + int address_subreg_nr; + int indirect_offset; /* XXX */ + + int swizzle_set; + int swizzle_x, swizzle_y, swizzle_z, swizzle_w; + + uint32_t imm32; /* only set if reg_file == BRW_IMMEDIATE_VALUE */ +} src_operand; + +/** + * This structure is just the list container for instructions accumulated by + * the parser. + */ +struct brw_program_instruction { + struct brw_instruction instruction; + struct brw_program_instruction *next; +}; + +/** + * This structure is a list of instructions. It is the final output of the + * parser. + */ +struct brw_program { + struct brw_program_instruction *first; +}; + +extern struct brw_program compiled_program; + +int yyparse(void); +int yylex(void); + +char * +lex_text(void); diff --git a/assembler/src/gram.y b/assembler/src/gram.y new file mode 100644 index 00000000..36fd6366 --- /dev/null +++ b/assembler/src/gram.y @@ -0,0 +1,1322 @@ +%{ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Eric Anholt <eric@anholt.net> + * + */ + +#include <stdio.h> +#include <string.h> +#include "gen4asm.h" +#include "brw_defines.h" + +%} + +%start ROOT + +%union { + char *s; + int integer; + double number; + struct brw_instruction instruction; + struct brw_program program; + struct region { + int vert_stride, width, horiz_stride; + } region; + struct direct_reg { + int reg_file, reg_nr, subreg_nr; + } direct_reg; + struct indirect_reg { + int reg_file, address_subreg_nr, indirect_offset; + } indirect_reg; + + double imm32; + + struct dst_operand dst_operand; + struct src_operand src_operand; +} + +%token SEMICOLON +%token LPAREN RPAREN +%token LANGLE RANGLE +%token LCURLY RCURLY +%token LSQUARE RSQUARE +%token COMMA +%token DOT +%token PLUS MINUS ABS + +%token <integer> TYPE_UD, TYPE_D, TYPE_UW, TYPE_W, TYPE_UB, TYPE_B, +%token <integer> TYPE_VF, TYPE_HF, TYPE_V, TYPE_F + +%token ALIGN1 ALIGN16 SECHALF COMPR SWITCH ATOMIC NODDCHK NODDCLR +%token MASK_DISABLE BREAKPOINT EOT + +%token ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H +%token <integer> GENREG MSGREG ADDRESSREG ACCREG FLAGREG +%token <integer> MASKREG AMASK IMASK LMASK CMASK +%token <integer> MASKSTACKREG LMS IMS MASKSTACKDEPTHREG IMSD LMSD +%token <integer> NOTIFYREG STATEREG CONTROLREG IPREG +%token GENREGFILE MSGREGFILE + +%token <integer> MOV FRC RNDU RNDD RNDE RNDZ NOT LZD +%token <integer> MUL MAC MACH LINE SAD2 SADA2 DP4 DPH DP3 DP2 +%token <integer> AVG ADD SEL AND OR XOR SHR SHL ASR CMP CMPN +%token <integer> SEND NOP JMPI IF IFF WHILE SEND ELSE BREAK CONT HALT MSAVE +%token <integer> PUSH MREST POP WAIT DO ENDIF ILLEGAL + +%token NULL_TOKEN MATH SAMPLER GATEWAY READ WRITE URB THREAD_SPAWNER + +%token MSGLEN RETURNLEN +%token <integer> ALLOCATE USED COMPLETE TRANSPOSE INTERLEAVE +%token SATURATE X Y Z W + +%token <integer> INTEGER +%token <number> NUMBER + +%token <integer> INV LOG EXP SQRT RSQ POW SIN COS SINCOS INTDIV INTMOD +%token <integer> INTDIVMOD +%token SIGNED SCALAR + +%token <integer> X Y Z W + +%type <instruction> instruction unaryinstruction binaryinstruction +%type <instruction> binaryaccinstruction triinstruction sendinstruction +%type <instruction> specialinstruction +%type <instruction> msgtarget +%type <instruction> instoptions instoption_list predicate +%type <program> instrseq +%type <integer> instoption +%type <integer> unaryop binaryop binaryaccop +%type <integer> conditionalmodifier saturate negate abs chansel +%type <integer> writemask_x writemask_y writemask_z writemask_w +%type <integer> regtype srcimmtype execsize dstregion immaddroffset +%type <integer> subregnum sampler_datatype +%type <integer> urb_swizzle urb_allocate urb_used urb_complete +%type <integer> math_function math_signed math_scalar +%type <integer> predctrl predstate +%type <region> region region_wh indirectregion +%type <direct_reg> directgenreg directmsgreg addrreg accreg flagreg maskreg +%type <direct_reg> maskstackreg maskstackdepthreg notifyreg +%type <direct_reg> statereg controlreg ipreg nullreg +%type <direct_reg> dstoperandex_typed srcarchoperandex_typed +%type <indirect_reg> indirectgenreg indirectmsgreg addrparam +%type <integer> mask_subreg maskstack_subreg maskstackdepth_subreg +%type <imm32> imm32 +%type <dst_operand> dst dstoperand dstoperandex dstreg post_dst writemask +%type <src_operand> directsrcoperand srcarchoperandex directsrcaccoperand +%type <src_operand> indirectsrcoperand +%type <src_operand> src srcimm imm32reg payload srcacc srcaccimm swizzle +%% + +ROOT: instrseq + { + compiled_program = $1; + } +; + +instrseq: instruction SEMICOLON instrseq + { + struct brw_program_instruction *list_entry = + calloc(sizeof(struct brw_program_instruction), 1); + list_entry->instruction = $1; + + list_entry->next = $3.first; + $3.first = list_entry; + + $$ = $3; + } + | instruction SEMICOLON + { + struct brw_program_instruction *list_entry = + calloc(sizeof(struct brw_program_instruction), 1); + list_entry->instruction = $1; + + list_entry->next = NULL; + + $$.first = list_entry; + } + | error SEMICOLON instrseq + { + $$ = $3; + } +; + +/* 1.4.1: Instruction groups */ +instruction: unaryinstruction + | binaryinstruction + | binaryaccinstruction + | triinstruction + | specialinstruction +; + +unaryinstruction: + predicate unaryop conditionalmodifier saturate execsize + dst srcaccimm instoptions + { + bzero(&$$, sizeof($$)); + $$.header.opcode = $2; + $$.header.destreg__conditionalmod = $3; + $$.header.saturate = $4; + $$.header.execution_size = $5; + set_instruction_options(&$$, &$8); + set_instruction_predicate(&$$, &$1); + if (set_instruction_dest(&$$, &$6) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$7) != 0) + YYERROR; + } +; + +unaryop: MOV | FRC | RNDU | RNDD | RNDE | RNDZ | NOT | LZD +; + +binaryinstruction: + predicate binaryop conditionalmodifier saturate execsize + dst src srcimm instoptions + { + bzero(&$$, sizeof($$)); + $$.header.opcode = $2; + $$.header.destreg__conditionalmod = $3; + $$.header.saturate = $4; + $$.header.execution_size = $5; + set_instruction_options(&$$, &$9); + set_instruction_predicate(&$$, &$1); + if (set_instruction_dest(&$$, &$6) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$7) != 0) + YYERROR; + if (set_instruction_src1(&$$, &$8) != 0) + YYERROR; + } +; + +binaryop: MUL | MAC | MACH | LINE | SAD2 | SADA2 | DP4 | DPH | DP3 | DP2 +; + +binaryaccinstruction: + predicate binaryaccop conditionalmodifier saturate execsize + dst srcacc srcimm instoptions + { + bzero(&$$, sizeof($$)); + $$.header.opcode = $2; + $$.header.destreg__conditionalmod = $3; + $$.header.saturate = $4; + $$.header.execution_size = $5; + set_instruction_options(&$$, &$9); + set_instruction_predicate(&$$, &$1); + if (set_instruction_dest(&$$, &$6) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$7) != 0) + YYERROR; + if (set_instruction_src1(&$$, &$8) != 0) + YYERROR; + } +; + +binaryaccop: AVG | ADD | SEL | AND | OR | XOR | SHR | SHL | ASR | CMP | CMPN +; + +triinstruction: sendinstruction +; + +sendinstruction: predicate SEND execsize INTEGER post_dst payload msgtarget + MSGLEN INTEGER RETURNLEN INTEGER instoptions + { + /* Send instructions are messy. The first argument is the + * post destination -- the grf register that the response + * starts from. The second argument is the current + * destination, which is the start of the message arguments + * to the shared function, and where src0 payload is loaded + * to if not null. The payload is typically based on the + * grf 0 thread payload of your current thread, and is + * implicitly loaded if non-null. + */ + bzero(&$$, sizeof($$)); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.header.destreg__conditionalmod = $4; /* msg reg index */ + set_instruction_predicate(&$$, &$1); + if (set_instruction_dest(&$$, &$5) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$6) != 0) + YYERROR; + $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; + $$.bits1.da1.src1_reg_type = BRW_REGISTER_TYPE_D; + $$.bits3.generic = $7.bits3.generic; + $$.bits3.generic.msg_length = $9; + $$.bits3.generic.response_length = $11; + $$.bits3.generic.end_of_thread = + $12.bits3.generic.end_of_thread; + } +; + +branchloopop: IF | IFF | WHILE +; + +breakop: BREAK | CONT | WAIT +; + +maskpushop: MSAVE | PUSH +; + +specialinstruction: NOP + { + bzero(&$$, sizeof($$)); + $$.header.opcode = $1; + } +; + +/* XXX! */ +payload: directsrcoperand +; + +post_dst: dst +; + +msgtarget: NULL_TOKEN + { + $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_NULL; + } + | SAMPLER LPAREN INTEGER COMMA INTEGER COMMA + sampler_datatype RPAREN + { + $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_SAMPLER; + $$.bits3.sampler.binding_table_index = $3; + $$.bits3.sampler.sampler = $5; + switch ($7) { + case TYPE_F: + $$.bits3.sampler.return_format = + BRW_SAMPLER_RETURN_FORMAT_FLOAT32; + break; + case TYPE_UD: + $$.bits3.sampler.return_format = + BRW_SAMPLER_RETURN_FORMAT_UINT32; + break; + case TYPE_D: + $$.bits3.sampler.return_format = + BRW_SAMPLER_RETURN_FORMAT_SINT32; + break; + } + } + | MATH math_function saturate math_signed math_scalar + { + $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_MATH; + $$.bits3.math.function = $2; + if ($3 == BRW_INSTRUCTION_SATURATE) + $$.bits3.math.saturate = 1; + else + $$.bits3.math.saturate = 0; + $$.bits3.math.int_type = $4; + $$.bits3.math.precision = BRW_MATH_PRECISION_FULL; + $$.bits3.math.data_type = $5; + } + | GATEWAY + { + $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_GATEWAY; + } + | READ + { + $$.bits3.generic.msg_target = + BRW_MESSAGE_TARGET_DATAPORT_READ; + } + | WRITE LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA + INTEGER RPAREN + { + $$.bits3.generic.msg_target = + BRW_MESSAGE_TARGET_DATAPORT_WRITE; + $$.bits3.dp_write.binding_table_index = $3; + /* The msg control field of brw_struct.h is split into + * msg control and pixel_scoreboard_clear, even though + * pixel_scoreboard_clear isn't common to all write messages. + */ + $$.bits3.dp_write.pixel_scoreboard_clear = ($5 & 0x8) >> 3; + $$.bits3.dp_write.msg_control = $5 & 0x7; + $$.bits3.dp_write.msg_type = $7; + $$.bits3.dp_write.send_commit_msg = $9; + } + | URB INTEGER urb_swizzle urb_allocate urb_used urb_complete + { + $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_URB; + $$.bits3.urb.opcode = BRW_URB_OPCODE_WRITE; + $$.bits3.urb.offset = $2; + $$.bits3.urb.swizzle_control = $3; + $$.bits3.urb.pad = 0; + $$.bits3.urb.allocate = $4; + $$.bits3.urb.used = $5; + $$.bits3.urb.complete = $6; + } + | THREAD_SPAWNER + { + $$.bits3.generic.msg_target = + BRW_MESSAGE_TARGET_THREAD_SPAWNER; + } +; + +urb_allocate: ALLOCATE { $$ = 1; } + | /* empty */ { $$ = 0; } +; + +urb_used: USED { $$ = 1; } + | /* empty */ { $$ = 0; } +; + +urb_complete: COMPLETE { $$ = 1; } + | /* empty */ { $$ = 0; } +; + +urb_swizzle: TRANSPOSE { $$ = BRW_URB_SWIZZLE_TRANSPOSE; } + | INTERLEAVE { $$ = BRW_URB_SWIZZLE_INTERLEAVE; } + | /* empty */ { $$ = BRW_URB_SWIZZLE_NONE; } +; + +sampler_datatype: + TYPE_F + | TYPE_UD + | TYPE_D +; + +math_function: INV | LOG | EXP | SQRT | POW | SIN | COS | SINCOS | INTDIV + | INTMOD | INTDIVMOD +; + +math_signed: /* empty */ { $$ = 0; } + | SIGNED { $$ = 1; } +; + +math_scalar: /* empty */ { $$ = 0; } + | SCALAR { $$ = 1; } +; + +/* 1.4.2: Destination register */ + +dst: dstoperand | dstoperandex +; + +dstoperand: dstreg dstregion writemask regtype + { + /* Returns an instruction with just the destination register + * filled in. + */ + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.horiz_stride = $2; + $$.writemask_set = $3.writemask_set; + $$.writemask = $3.writemask; + $$.reg_type = $4; + } +; + +/* The dstoperandex returns an instruction with just the destination register + * filled in. + */ +dstoperandex: dstoperandex_typed dstregion regtype + { + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.horiz_stride = $2; + $$.reg_type = $3; + } + | maskstackreg + { + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.horiz_stride = 1; + $$.reg_type = BRW_REGISTER_TYPE_UW; + } + | controlreg + { + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.horiz_stride = 1; + $$.reg_type = BRW_REGISTER_TYPE_UD; + } + | ipreg + { + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.horiz_stride = 1; + $$.reg_type = BRW_REGISTER_TYPE_UD; + } + | nullreg + { + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.horiz_stride = 1; + $$.reg_type = BRW_REGISTER_TYPE_F; + } +; + +dstoperandex_typed: accreg | flagreg | addrreg | maskreg +; + +/* Returns a partially complete destination register consisting of the + * direct or indirect register addressing fields, but not stride or writemask. + */ +dstreg: directgenreg + { + $$.address_mode = BRW_ADDRESS_DIRECT; + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + } + | directmsgreg + { + $$.address_mode = BRW_ADDRESS_DIRECT; + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + } + | indirectgenreg + { + $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + $$.reg_file = $1.reg_file; + $$.address_subreg_nr = $1.address_subreg_nr; + $$.indirect_offset = $1.indirect_offset; + } + | indirectmsgreg + { + $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + $$.reg_file = $1.reg_file; + $$.address_subreg_nr = $1.address_subreg_nr; + $$.indirect_offset = $1.indirect_offset; + } +; + +/* 1.4.3: Source register */ +srcaccimm: srcacc | imm32reg +; + +srcacc: directsrcaccoperand | indirectsrcoperand +; + +srcimm: directsrcoperand | imm32reg +; + +imm32reg: imm32 srcimmtype + { + union { + int i; + float f; + } intfloat; + + $$.reg_file = BRW_IMMEDIATE_VALUE; + $$.reg_type = $2; + switch ($2) { + case BRW_REGISTER_TYPE_UD: + $$.imm32 = $1; + break; + case BRW_REGISTER_TYPE_D: + $$.imm32 = $1; + break; + case BRW_REGISTER_TYPE_UW: + $$.imm32 = $1; + break; + case BRW_REGISTER_TYPE_W: + $$.imm32 = $1; + break; + case BRW_REGISTER_TYPE_UB: + /* There is no native byte immediate type */ + $$.imm32 = (unsigned int)$1; + $$.reg_type = BRW_REGISTER_TYPE_UD; + break; + case BRW_REGISTER_TYPE_B: + /* There is no native byte immediate type */ + $$.imm32 = (int)$1; + $$.reg_type = BRW_REGISTER_TYPE_D; + break; + case BRW_REGISTER_TYPE_F: + intfloat.f = $1; + $$.imm32 = intfloat.i; + break; + default: + fprintf(stderr, "unknown immediate type %d\n", $2); + YYERROR; + } + } +; + +directsrcaccoperand: directsrcoperand + | accreg regtype + { + set_direct_src_operand(&$$, &$1, $2); + } +; + +/* Returns a source operand in the src0 fields of an instruction. */ +srcarchoperandex: srcarchoperandex_typed region regtype + { + $$.reg_file = $1.reg_file; + $$.reg_type = $3; + $$.subreg_nr = $1.subreg_nr; + $$.reg_nr = $1.reg_nr; + $$.vert_stride = $2.vert_stride; + $$.width = $2.width; + $$.horiz_stride = $2.horiz_stride; + $$.negate = 0; + $$.abs = 0; + } + | maskstackreg + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UB); + } + | controlreg + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); + } + | statereg + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); + } + | notifyreg + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); + } + | ipreg + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); + } + | nullreg + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); + } +; + +srcarchoperandex_typed: flagreg | addrreg | maskreg +; + +src: directsrcoperand | indirectsrcoperand +; + +directsrcoperand: + negate abs directgenreg region regtype swizzle + { + $$.address_mode = BRW_ADDRESS_DIRECT; + $$.reg_file = $3.reg_file; + $$.reg_nr = $3.reg_nr; + $$.subreg_nr = $3.subreg_nr; + $$.reg_type = $5; + $$.vert_stride = $4.vert_stride; + $$.width = $4.width; + $$.horiz_stride = $4.horiz_stride; + $$.negate = $1; + $$.abs = $2; + $$.swizzle_set = $6.swizzle_set; + $$.swizzle_x = $6.swizzle_x; + $$.swizzle_y = $6.swizzle_y; + $$.swizzle_z = $6.swizzle_z; + $$.swizzle_w = $6.swizzle_w; + } + | srcarchoperandex +; + +indirectsrcoperand: + negate abs indirectgenreg indirectregion regtype swizzle + { + $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + $$.reg_file = $3.reg_file; + $$.address_subreg_nr = $3.address_subreg_nr; + $$.indirect_offset = $3.indirect_offset; + $$.reg_type = $5; + $$.vert_stride = $4.vert_stride; + $$.width = $4.width; + $$.horiz_stride = $4.horiz_stride; + $$.negate = $1; + $$.abs = $2; + $$.swizzle_set = $6.swizzle_set; + $$.swizzle_x = $6.swizzle_x; + $$.swizzle_y = $6.swizzle_y; + $$.swizzle_z = $6.swizzle_z; + $$.swizzle_w = $6.swizzle_w; + } +; + +/* 1.4.4: Address Registers */ +/* Returns a partially-completed indirect_reg consisting of the address + * register fields for register-indirect access. + */ +addrparam: addrreg immaddroffset + { + if ($2 < -512 || $2 > 511) { + fprintf(stderr, "Address immediate offset %d out of" + "range\n", $2); + YYERROR; + } + $$.address_subreg_nr = $1.subreg_nr; + $$.indirect_offset = $2; + } +; + +/* The immaddroffset provides an immediate offset value added to the addresses + * from the address register in register-indirect register access. + */ +immaddroffset: /* empty */ { $$ = 0; } + | INTEGER +; + + +/* 1.4.5: Register files and register numbers */ +subregnum: DOT INTEGER + { + $$ = $2; + } + | + { + /* Default to subreg 0 if unspecified. */ + $$ = 0; + } +; + +directgenreg: GENREG subregnum + { + $$.reg_file = BRW_GENERAL_REGISTER_FILE; + $$.reg_nr = $1; + $$.subreg_nr = $2; + } +; + +indirectgenreg: GENREGFILE LSQUARE addrparam RSQUARE + { + $$.reg_file = BRW_GENERAL_REGISTER_FILE; + $$.address_subreg_nr = $3.address_subreg_nr; + $$.indirect_offset = $3.indirect_offset; + } +; + +directmsgreg: MSGREG subregnum + { + $$.reg_file = BRW_MESSAGE_REGISTER_FILE; + $$.reg_nr = $1; + $$.subreg_nr = $2; + } +; + +indirectmsgreg: MSGREGFILE LSQUARE addrparam RSQUARE + { + $$.reg_file = BRW_MESSAGE_REGISTER_FILE; + $$.address_subreg_nr = $3.address_subreg_nr; + $$.indirect_offset = $3.indirect_offset; + } +; + +addrreg: ADDRESSREG subregnum + { + if ($1 != 0) { + fprintf(stderr, + "address register number %d out of range", $1); + YYERROR; + } + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_ADDRESS | $1; + $$.subreg_nr = $2; + } +; + +accreg: ACCREG subregnum + { + if ($1 > 1) { + fprintf(stderr, + "accumulator register number %d out of range", $1); + YYERROR; + } + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_ACCUMULATOR | $1; + $$.subreg_nr = $2; + } +; + +flagreg: FLAGREG + { + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_FLAG | 0; + $$.subreg_nr = $1; + } +; + +maskreg: MASKREG subregnum + { + if ($1 > 0) { + fprintf(stderr, + "mask register number %d out of range", $1); + YYERROR; + } + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK; + $$.subreg_nr = $2; + } + | mask_subreg + { + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK; + $$.subreg_nr = $1; + } +; + +mask_subreg: AMASK | IMASK | LMASK | CMASK +; + +maskstackreg: MASKSTACKREG subregnum + { + if ($1 > 0) { + fprintf(stderr, + "mask stack register number %d out of range", $1); + YYERROR; + } + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK_STACK; + $$.subreg_nr = $2; + } + | maskstack_subreg + { + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK_STACK; + $$.subreg_nr = $1; + } +; + +maskstack_subreg: IMS | LMS +; + +maskstackdepthreg: MASKSTACKDEPTHREG subregnum + { + if ($1 > 0) { + fprintf(stderr, + "mask stack register number %d out of range", $1); + YYERROR; + } + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK_STACK_DEPTH; + $$.subreg_nr = $2; + } + | maskstackdepth_subreg + { + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK_STACK_DEPTH; + $$.subreg_nr = $1; + } +; + +maskstackdepth_subreg: IMSD | LMSD +; + +notifyreg: NOTIFYREG + { + if ($1 > 1) { + fprintf(stderr, + "notification register number %d out of range", + $1); + YYERROR; + } + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_NOTIFICATION_COUNT; + $$.subreg_nr = 0; + } +; + +statereg: STATEREG subregnum + { + if ($1 > 0) { + fprintf(stderr, + "state register number %d out of range", $1); + YYERROR; + } + if ($2 > 1) { + fprintf(stderr, + "state subregister number %d out of range", $1); + YYERROR; + } + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_STATE | $1; + $$.subreg_nr = $2; + } +; + +controlreg: CONTROLREG subregnum + { + if ($1 > 0) { + fprintf(stderr, + "control register number %d out of range", $1); + YYERROR; + } + if ($2 > 2) { + fprintf(stderr, + "control subregister number %d out of range", $1); + YYERROR; + } + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_CONTROL | $1; + $$.subreg_nr = $2; + } +; + +ipreg: IPREG + { + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_IP; + $$.subreg_nr = 0; + } +; + +nullreg: NULL_TOKEN + { + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_NULL; + $$.subreg_nr = 0; + } +; + +/* 1.4.7: Regions */ +dstregion: LANGLE INTEGER RANGLE + { + /* Returns a value for a horiz_stride field of an + * instruction. + */ + if ($2 != 1 && $2 != 2 && $2 != 4) { + fprintf(stderr, "Invalid horiz size %d\n", $2); + } + $$ = ffs($2); + } +; + +region: LANGLE INTEGER COMMA INTEGER COMMA INTEGER RANGLE + { + $$.vert_stride = ffs($2); + $$.width = ffs($4) - 1; + $$.horiz_stride = ffs($6); + } +; + +/* region_wh is used in specifying indirect operands where rather than having + * a vertical stride, you use subsequent address registers to get a new base + * offset for the next row. + */ +region_wh: LANGLE INTEGER COMMA INTEGER RANGLE + { + $$.vert_stride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL; + $$.width = ffs($2) - 1; + $$.horiz_stride = ffs($4); + } +; + +indirectregion: region | region_wh +; + +/* 1.4.8: Types */ + +/* regtype returns an integer register type suitable for inserting into an + * instruction. + */ +regtype: TYPE_F { $$ = BRW_REGISTER_TYPE_F; } + | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; } + | TYPE_D { $$ = BRW_REGISTER_TYPE_D; } + | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; } + | TYPE_W { $$ = BRW_REGISTER_TYPE_W; } + | TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; } + | TYPE_B { $$ = BRW_REGISTER_TYPE_B; } +; + +/* XXX: Add TYPE_VF and TYPE_HF */ +srcimmtype: regtype +; + +/* 1.4.10: Swizzle control */ +/* Returns the swizzle control for an align16 instruction's source operand + * in the src0 fields. + */ +swizzle: /* empty */ + { + $$.swizzle_set = 0; + $$.swizzle_x = BRW_CHANNEL_X; + $$.swizzle_y = BRW_CHANNEL_Y; + $$.swizzle_z = BRW_CHANNEL_Z; + $$.swizzle_w = BRW_CHANNEL_W; + } + | DOT chansel + { + $$.swizzle_set = 1; + $$.swizzle_x = $2; + $$.swizzle_y = $2; + $$.swizzle_z = $2; + $$.swizzle_w = $2; + } + | DOT chansel chansel chansel chansel + { + $$.swizzle_set = 1; + $$.swizzle_x = $2; + $$.swizzle_y = $3; + $$.swizzle_z = $4; + $$.swizzle_w = $5; + } +; + +chansel: X | Y | Z | W +; + +/* 1.4.9: Write mask */ +/* Returns a partially completed dst_operand, with just the writemask bits + * filled out. + */ +writemask: /* empty */ + { + $$.writemask_set = 0; + $$.writemask = 0xf; + } + | DOT writemask_x writemask_y writemask_z writemask_w + { + $$.writemask_set = 1; + $$.writemask = $2 | $3 | $4 | $5; + } + +writemask_x: /* empty */ { $$ = 0; } + | X { $$ = 1 << BRW_CHANNEL_X; } + +writemask_y: /* empty */ { $$ = 0; } + | Y { $$ = 1 << BRW_CHANNEL_Y; } + +writemask_z: /* empty */ { $$ = 0; } + | Z { $$ = 1 << BRW_CHANNEL_Z; } + +writemask_w: /* empty */ { $$ = 0; } + | W { $$ = 1 << BRW_CHANNEL_W; } + +/* 1.4.11: Immediate values */ +imm32: INTEGER { $$ = $1; } + | NUMBER { $$ = $1; } +; + +/* 1.4.12: Predication and modifiers */ +predicate: /* empty */ + { + $$.header.predicate_control = BRW_PREDICATE_NONE; + $$.bits2.da1.flag_reg_nr = 0; + $$.header.predicate_inverse = 0; + } + | LPAREN predstate flagreg predctrl RPAREN + { + $$.header.predicate_control = $4; + /* XXX: Should deal with erroring when the user tries to + * set a predicate for one flag register and conditional + * modification on the other flag register. + */ + $$.bits2.da1.flag_reg_nr = $3.subreg_nr; + $$.header.predicate_inverse = $2; + } +; + +predstate: /* empty */ { $$ = 0; } + | PLUS { $$ = 0; } + | MINUS { $$ = 1; } +; + +predctrl: /* empty */ { $$ = BRW_PREDICATE_NONE; } + | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; } + | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; } + | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; } + | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; } + | ANY2H { $$ = BRW_PREDICATE_ALIGN1_ANY2H; } + | ALL2H { $$ = BRW_PREDICATE_ALIGN1_ALL2H; } + | ANY4H { $$ = BRW_PREDICATE_ALIGN1_ANY4H; } + | ALL4H { $$ = BRW_PREDICATE_ALIGN1_ALL4H; } + | ANY8H { $$ = BRW_PREDICATE_ALIGN1_ANY8H; } + | ALL8H { $$ = BRW_PREDICATE_ALIGN1_ALL8H; } + | ANY16H { $$ = BRW_PREDICATE_ALIGN1_ANY16H; } + | ALL16H { $$ = BRW_PREDICATE_ALIGN1_ALL16H; } +; + +negate: /* empty */ { $$ = 0; } + | MINUS { $$ = 1; } +; + +abs: /* empty */ { $$ = 0; } + | ABS { $$ = 1; } +; + +execsize: LPAREN INTEGER RPAREN + { + /* Returns a value for the execution_size field of an + * instruction. + */ + if ($2 != 1 && $2 != 2 && $2 != 4 && $2 != 8 && $2 != 16 && + $2 != 32) { + fprintf(stderr, "Invalid execution size %d\n", $2); + YYERROR; + } + $$ = ffs($2) - 1; + } +; + +saturate: /* empty */ { $$ = BRW_INSTRUCTION_NORMAL; } + | DOT SATURATE { $$ = BRW_INSTRUCTION_SATURATE; } +; + +conditionalmodifier: { $$ = 0; } +; + +/* 1.4.13: Instruction options */ +instoptions: LCURLY instoption_list RCURLY + { $$ = $2; } +; + +instoption_list: instoption instoption_list + { + $$ = $2; + switch ($1) { + case ALIGN1: + $$.header.access_mode = BRW_ALIGN_1; + break; + case ALIGN16: + $$.header.access_mode = BRW_ALIGN_16; + break; + case SECHALF: + $$.header.compression_control |= BRW_COMPRESSION_2NDHALF; + break; + case COMPR: + $$.header.compression_control |= + BRW_COMPRESSION_COMPRESSED; + break; + case SWITCH: + $$.header.thread_control |= BRW_THREAD_SWITCH; + break; + case ATOMIC: + $$.header.thread_control |= BRW_THREAD_ATOMIC; + break; + case NODDCHK: + $$.header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED; + break; + case NODDCLR: + $$.header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED; + break; + case MASK_DISABLE: + $$.header.mask_control = BRW_MASK_DISABLE; + break; + case BREAKPOINT: + $$.header.debug_control = BRW_DEBUG_BREAKPOINT; + break; + case EOT: + /* XXX: EOT shouldn't be an instoption, I don't think */ + $$.bits3.generic.end_of_thread = 1; + break; + } + } + | /* empty, header defaults to zeroes. */ + { + bzero(&$$, sizeof($$)); + } +; + +instoption: ALIGN1 { $$ = ALIGN1; } + | ALIGN16 { $$ = ALIGN16; } + | SECHALF { $$ = SECHALF; } + | COMPR { $$ = COMPR; } + | SWITCH { $$ = SWITCH; } + | ATOMIC { $$ = ATOMIC; } + | NODDCHK { $$ = NODDCHK; } + | NODDCLR { $$ = NODDCLR; } + | MASK_DISABLE { $$ = MASK_DISABLE; } + | BREAKPOINT { $$ = BREAKPOINT; } + | EOT { $$ = EOT; } +; + +%% +extern int yylineno; + +void yyerror (char *msg) +{ + fprintf(stderr, "parse error \"%s\" at line %d, token \"%s\"\n", + msg, yylineno, lex_text()); +} + +/** + * Fills in the destination register information in instr from the bits in dst. + */ +int set_instruction_dest(struct brw_instruction *instr, + struct dst_operand *dest) +{ + if (dest->address_mode == BRW_ADDRESS_DIRECT && + instr->header.access_mode == BRW_ALIGN_1) { + instr->bits1.da1.dest_reg_file = dest->reg_file; + instr->bits1.da1.dest_reg_type = dest->reg_type; + instr->bits1.da1.dest_subreg_nr = dest->subreg_nr; + instr->bits1.da1.dest_reg_nr = dest->reg_nr; + instr->bits1.da1.dest_horiz_stride = dest->horiz_stride; + instr->bits1.da1.dest_address_mode = dest->address_mode; + if (dest->writemask_set) { + fprintf(stderr, "error: write mask set in align1 " + "instruction\n"); + return 1; + } + } else if (dest->address_mode == BRW_ADDRESS_DIRECT) { + instr->bits1.da16.dest_reg_file = dest->reg_file; + instr->bits1.da16.dest_reg_type = dest->reg_type; + instr->bits1.da16.dest_subreg_nr = dest->subreg_nr; + instr->bits1.da16.dest_reg_nr = dest->reg_nr; + instr->bits1.da16.dest_address_mode = dest->address_mode; + instr->bits1.da16.dest_writemask = dest->writemask; + } else if (instr->header.access_mode == BRW_ALIGN_1) { + instr->bits1.ia1.dest_reg_file = dest->reg_file; + instr->bits1.ia1.dest_reg_type = dest->reg_type; + instr->bits1.ia1.dest_subreg_nr = dest->address_subreg_nr; + instr->bits1.ia1.dest_horiz_stride = dest->horiz_stride; + instr->bits1.ia1.dest_indirect_offset = dest->indirect_offset; + instr->bits1.ia1.dest_address_mode = dest->address_mode; + if (dest->writemask_set) { + fprintf(stderr, "error: write mask set in align1 " + "instruction\n"); + return 1; + } + } else { + instr->bits1.ia16.dest_reg_file = dest->reg_file; + instr->bits1.ia16.dest_reg_type = dest->reg_type; + instr->bits1.ia16.dest_subreg_nr = dest->address_subreg_nr; + instr->bits1.ia16.dest_writemask = dest->writemask; + instr->bits1.ia16.dest_indirect_offset = dest->indirect_offset; + instr->bits1.ia16.dest_address_mode = dest->address_mode; + } + + return 0; +} + +/* Sets the first source operand for the instruction. Returns 0 on success. */ +int set_instruction_src0(struct brw_instruction *instr, + struct src_operand *src) +{ + instr->bits1.da1.src0_reg_file = src->reg_file; + instr->bits1.da1.src0_reg_type = src->reg_type; + if (src->reg_file == BRW_IMMEDIATE_VALUE) { + instr->bits3.ud = src->imm32; + } else if (instr->header.access_mode == BRW_ALIGN_1) { + instr->bits2.da1.src0_subreg_nr = src->subreg_nr; + instr->bits2.da1.src0_reg_nr = src->reg_nr; + instr->bits2.da1.src0_vert_stride = src->vert_stride; + instr->bits2.da1.src0_width = src->width; + instr->bits2.da1.src0_horiz_stride = src->horiz_stride; + instr->bits2.da1.src0_negate = src->negate; + instr->bits2.da1.src0_abs = src->abs; + instr->bits2.da1.src0_address_mode = src->address_mode; + if (src->swizzle_set) { + fprintf(stderr, "error: swizzle bits set in align1 " + "instruction\n"); + return 1; + } + } else { + instr->bits2.da16.src0_subreg_nr = src->subreg_nr; + instr->bits2.da16.src0_reg_nr = src->reg_nr; + instr->bits2.da16.src0_vert_stride = src->vert_stride; + instr->bits2.da16.src0_negate = src->negate; + instr->bits2.da16.src0_abs = src->abs; + instr->bits2.da16.src0_swz_x = src->swizzle_x; + instr->bits2.da16.src0_swz_y = src->swizzle_y; + instr->bits2.da16.src0_swz_z = src->swizzle_z; + instr->bits2.da16.src0_swz_w = src->swizzle_w; + instr->bits2.da16.src0_address_mode = src->address_mode; + } + + return 0; +} + +/* Sets the second source operand for the instruction. Returns 0 on success. + */ +int set_instruction_src1(struct brw_instruction *instr, + struct src_operand *src) +{ + instr->bits1.da1.src1_reg_file = src->reg_file; + instr->bits1.da1.src1_reg_type = src->reg_type; + if (src->reg_file == BRW_IMMEDIATE_VALUE) { + instr->bits3.ud = src->imm32; + } else if (instr->header.access_mode == BRW_ALIGN_1) { + instr->bits3.da1.src1_subreg_nr = src->subreg_nr; + instr->bits3.da1.src1_reg_nr = src->reg_nr; + instr->bits3.da1.src1_vert_stride = src->vert_stride; + instr->bits3.da1.src1_width = src->width; + instr->bits3.da1.src1_horiz_stride = src->horiz_stride; + instr->bits3.da1.src1_negate = src->negate; + instr->bits3.da1.src1_abs = src->abs; + if (src->address_mode != BRW_ADDRESS_DIRECT) { + fprintf(stderr, "error: swizzle bits set in align1 " + "instruction\n"); + return 1; + } + if (src->swizzle_set) { + fprintf(stderr, "error: swizzle bits set in align1 " + "instruction\n"); + return 1; + } + } else { + instr->bits3.da16.src1_subreg_nr = src->subreg_nr; + instr->bits3.da16.src1_reg_nr = src->reg_nr; + instr->bits3.da16.src1_vert_stride = src->vert_stride; + instr->bits3.da16.src1_negate = src->negate; + instr->bits3.da16.src1_abs = src->abs; + instr->bits3.da16.src1_swz_x = src->swizzle_x; + instr->bits3.da16.src1_swz_y = src->swizzle_y; + instr->bits3.da16.src1_swz_z = src->swizzle_z; + instr->bits3.da16.src1_swz_w = src->swizzle_w; + if (src->address_mode != BRW_ADDRESS_DIRECT) { + fprintf(stderr, "error: swizzle bits set in align1 " + "instruction\n"); + return 1; + } + } + + return 0; +} + +void set_instruction_options(struct brw_instruction *instr, + struct brw_instruction *options) +{ + /* XXX: more instr options */ + instr->header.access_mode = options->header.access_mode; + instr->header.mask_control = options->header.mask_control; + instr->header.dependency_control = options->header.dependency_control; + instr->header.compression_control = + options->header.compression_control; +} + +void set_instruction_predicate(struct brw_instruction *instr, + struct brw_instruction *predicate) +{ + instr->header.predicate_control = predicate->header.predicate_control; + instr->header.predicate_inverse = predicate->header.predicate_inverse; + instr->bits2.da1.flag_reg_nr = predicate->bits2.da1.flag_reg_nr; +} + +void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg, + int type) +{ + bzero(src, sizeof(*src)); + src->reg_file = reg->reg_file; + src->reg_type = type; + src->subreg_nr = reg->subreg_nr; + src->reg_nr = reg->reg_nr; + src->vert_stride = 0; + src->width = 0; + src->horiz_stride = 1; + src->negate = 0; + src->abs = 0; +} diff --git a/assembler/src/lex.l b/assembler/src/lex.l new file mode 100644 index 00000000..97b9c3d2 --- /dev/null +++ b/assembler/src/lex.l @@ -0,0 +1,324 @@ +%option yylineno +%{ +#include "gen4asm.h" +#include "gram.h" +#include "brw_defines.h" + +int saved_state = INITIAL; + +%} +%x BLOCK_COMMENT + +%% +\/\/.*[\r\n] { } /* eat up single-line comments */ + + /* eat up multi-line comments, non-nesting. */ +\/\* { + saved_state = YYSTATE; + BEGIN(BLOCK_COMMENT); +} +<BLOCK_COMMENT>\*\/ { + BEGIN(saved_state); +} +<BLOCK_COMMENT>. { } +<BLOCK_COMMENT>[\r\n] { } + + /* used for both null send and null register. */ +"null" { return NULL_TOKEN; } + + /* opcodes */ +"mov" { yylval.integer = BRW_OPCODE_MOV; return MOV; } +"frc" { yylval.integer = BRW_OPCODE_FRC; return FRC; } +"rndu" { yylval.integer = BRW_OPCODE_RNDU; return RNDU; } +"rndd" { yylval.integer = BRW_OPCODE_RNDD; return RNDD; } +"rnde" { yylval.integer = BRW_OPCODE_RNDE; return RNDE; } +"rndz" { yylval.integer = BRW_OPCODE_RNDZ; return RNDZ; } +"not" { yylval.integer = BRW_OPCODE_NOT; return NOT; } +"lzd" { yylval.integer = BRW_OPCODE_LZD; return LZD; } + +"mul" { yylval.integer = BRW_OPCODE_MUL; return MUL; } +"mac" { yylval.integer = BRW_OPCODE_MAC; return MAC; } +"mach" { yylval.integer = BRW_OPCODE_MACH; return MACH; } +"line" { yylval.integer = BRW_OPCODE_LINE; return LINE; } +"sad2" { yylval.integer = BRW_OPCODE_SAD2; return SAD2; } +"sada2" { yylval.integer = BRW_OPCODE_SADA2; return SADA2; } +"dp4" { yylval.integer = BRW_OPCODE_DP4; return DP4; } +"dph" { yylval.integer = BRW_OPCODE_DPH; return DPH; } +"dp3" { yylval.integer = BRW_OPCODE_DP3; return DP3; } +"dp2" { yylval.integer = BRW_OPCODE_DP2; return DP2; } + +"avg" { yylval.integer = BRW_OPCODE_AVG; return AVG; } +"add" { yylval.integer = BRW_OPCODE_ADD; return ADD; } +"sel" { yylval.integer = BRW_OPCODE_SEL; return SEL; } +"and" { yylval.integer = BRW_OPCODE_AND; return AND; } +"or" { yylval.integer = BRW_OPCODE_OR; return OR; } +"xor" { yylval.integer = BRW_OPCODE_XOR; return XOR; } +"shr" { yylval.integer = BRW_OPCODE_SHR; return SHR; } +"shl" { yylval.integer = BRW_OPCODE_SHL; return SHL; } +"asr" { yylval.integer = BRW_OPCODE_ASR; return ASR; } +"cmp" { yylval.integer = BRW_OPCODE_CMP; return CMP; } +"cmpn" { yylval.integer = BRW_OPCODE_CMPN; return CMPN; } + +"send" { yylval.integer = BRW_OPCODE_SEND; return SEND; } +"nop" { yylval.integer = BRW_OPCODE_NOP; return NOP; } +"jmpi" { yylval.integer = BRW_OPCODE_JMPI; return JMPI; } +"if" { yylval.integer = BRW_OPCODE_IF; return IF; } +"iff" { yylval.integer = BRW_OPCODE_IFF; return IFF; } +"while" { yylval.integer = BRW_OPCODE_NOP; return NOP; } +"send" { yylval.integer = BRW_OPCODE_SEND; return SEND; } +"else" { yylval.integer = BRW_OPCODE_ELSE; return ELSE; } +"break" { yylval.integer = BRW_OPCODE_BREAK; return BREAK; } +"cont" { yylval.integer = BRW_OPCODE_CONTINUE; return CONT; } +"halt" { yylval.integer = BRW_OPCODE_HALT; return HALT; } +"msave" { yylval.integer = BRW_OPCODE_MSAVE; return MSAVE; } +"push" { yylval.integer = BRW_OPCODE_PUSH; return PUSH; } +"mrest" { yylval.integer = BRW_OPCODE_MRESTORE; return MREST; } +"pop" { yylval.integer = BRW_OPCODE_POP; return POP; } +"wait" { yylval.integer = BRW_OPCODE_WAIT; return WAIT; } +"do" { yylval.integer = BRW_OPCODE_DO; return DO; } +"endif" { yylval.integer = BRW_OPCODE_ENDIF; return ENDIF; } + + /* send argument tokens */ +"mlen" { return MSGLEN; } +"rlen" { return RETURNLEN; } +"math" { return MATH; } +"sampler" { return SAMPLER; } +"gateway" { return GATEWAY; } +"read" { return READ; } +"write" { return WRITE; } +"urb" { return URB; } +"thread_spawner" { return THREAD_SPAWNER; } + +"allocate" { return ALLOCATE; } +"used" { return USED; } +"complete" { return COMPLETE; } +"transpose" { return TRANSPOSE; } +"interleave" { return INTERLEAVE; } + +";" { return SEMICOLON; } +"(" { return LPAREN; } +")" { return RPAREN; } +"<" { return LANGLE; } +">" { return RANGLE; } +"{" { return LCURLY; } +"}" { return RCURLY; } +"[" { return LSQUARE; } +"]" { return RSQUARE; } +"," { return COMMA; } +"." { return DOT; } +"+" { return PLUS; } +"-" { return MINUS; } +"(abs)" { return ABS; } + + /* Most register accesses are lexed as REGFILE[0-9]+, to prevent the register + * with subreg from being lexed as REGFILE NUMBER instead of + * REGISTER INTEGER DOT INTEGER like we want. The alternative was to use a + * start condition, which wasn't very clean-looking. + * + * However, this means we need to lex the general and message register file + * characters as well, for register-indirect access which is formatted + * like g[a#.#] or m[a#.#]. + */ +"acc"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return ACCREG; +} +"a"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return ADDRESSREG; +} +"m"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return MSGREG; +} +"m" { + return MSGREGFILE; +} +"mask"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return MASKREG; +} +"ms"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return MASKSTACKREG; +} +"msd"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return MASKSTACKDEPTHREG; +} +"n"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return NOTIFYREG; +} + /* Unlike other registers, flagreg returns the subreg number in the lvalue + * rather than the reg number, to avoid a shift/reduce conflict in the + * predicate control. + */ +"f0.[0-9]+" { + yylval.integer = atoi(yytext + 3); + return FLAGREG; +} +"f0" { + yylval.integer = 0; + return FLAGREG; +} +[gr][0-9]+ { + yylval.integer = atoi(yytext + 1); + return GENREG; +} +[gr] { + return GENREGFILE; +} +"cr"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return CONTROLREG; +} +"sr"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return STATEREG; +} +"ip" { + return IPREG; +} +"amask" { + yylval.integer = BRW_AMASK; + return AMASK; +} +"imask" { + yylval.integer = BRW_IMASK; + return IMASK; +} +"lmask" { + yylval.integer = BRW_LMASK; + return LMASK; +} +"cmask" { + yylval.integer = BRW_CMASK; + return CMASK; +} +"imsd" { + yylval.integer = 0; + return IMSD; +} +"lmsd" { + yylval.integer = 1; + return LMSD; +} +"ims" { + yylval.integer = 0; + return IMS; +} +"lms" { + yylval.integer = 16; + return LMS; +} + + /* + * Lexing of register types should probably require the ":" symbol specified + * in the BNF of the assembly, but our existing source didn't use that syntax. + */ +"UD" { return TYPE_UD; } +"D" { return TYPE_D; } +"UW" { return TYPE_UW; } +"W" { return TYPE_W; } +"UB" { return TYPE_UB; } +"B" { return TYPE_B; } +"F" { return TYPE_F; } + +"sat" { return SATURATE; } +"align1" { return ALIGN1; } +"align16" { return ALIGN16; } +"sechalf" { return SECHALF; } +"compr" { return COMPR; } +"switch" { return SWITCH; } +"atomic" { return ATOMIC; } +"noddchk" { return NODDCHK; } +"noddclr" { return NODDCLR; } +"mask_disable" { return MASK_DISABLE; } +"nomask" { return MASK_DISABLE; } +"breakpoint" { return BREAKPOINT; } +"EOT" { return EOT; } + + /* extended math functions */ +"inv" { yylval.integer = BRW_MATH_FUNCTION_INV; return SIN; } +"log" { yylval.integer = BRW_MATH_FUNCTION_LOG; return LOG; } +"exp" { yylval.integer = BRW_MATH_FUNCTION_EXP; return EXP; } +"sqrt" { yylval.integer = BRW_MATH_FUNCTION_SQRT; return SQRT; } +"rsq" { yylval.integer = BRW_MATH_FUNCTION_RSQ; return RSQ; } +"pow" { yylval.integer = BRW_MATH_FUNCTION_POW; return POW; } +"sin" { yylval.integer = BRW_MATH_FUNCTION_SIN; return SIN; } +"cos" { yylval.integer = BRW_MATH_FUNCTION_COS; return COS; } +"sincos" { yylval.integer = BRW_MATH_FUNCTION_SINCOS; return SINCOS; } +"intdiv" { + yylval.integer = BRW_MATH_FUNCTION_INT_DIV_QUOTIENT; + return INTDIV; +} +"intmod" { + yylval.integer = BRW_MATH_FUNCTION_INT_DIV_REMAINDER; + return INTMOD; +} +"intdivmod" { + yylval.integer = BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER; + return INTDIVMOD; +} + +"signed" { return SIGNED; } +"scalar" { return SCALAR; } + + /* predicate control */ +"any2h" { return ANY2H; } +"all2h" { return ALL2H; } +"any4h" { return ANY4H; } +"all4h" { return ALL4H; } +"any8h" { return ANY8H; } +"all8h" { return ALL8H; } +"any16h" { return ANY16H; } +"all16h" { return ALL16H; } + + /* channel selectors */ +"x" { + yylval.integer = BRW_CHANNEL_X; + return X; +} +"y" { + yylval.integer = BRW_CHANNEL_Y; + return Y; +} +"z" { + yylval.integer = BRW_CHANNEL_Z; + return Z; +} +"w" { + yylval.integer = BRW_CHANNEL_W; + return W; +} + +[0-9]* { + yylval.integer = atoi(yytext); + return INTEGER; +} + +<INITIAL>[-]?[0-9]+"."[0-9]+ { + yylval.number = strtod(yytext, NULL); + return NUMBER; +} + +[ \t\n]+ { } /* eat up whitespace */ + +. { + printf("parse error at line %d: unexpected \"%s\"\n", + yylineno, yytext); + exit(1); +} +%% + +char * +lex_text(void) +{ + return yytext; +} + +#ifndef yywrap +int yywrap() { return 1; } +#endif + diff --git a/assembler/src/main.c b/assembler/src/main.c new file mode 100644 index 00000000..0f1a50a9 --- /dev/null +++ b/assembler/src/main.c @@ -0,0 +1,100 @@ +/* -*- c-basic-offset: 8 -*- */ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Eric Anholt <eric@anholt.net> + * + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <getopt.h> + +#include "gen4asm.h" + +extern FILE *yyin; + +struct brw_program compiled_program; + +static const struct option longopts[] = { + { NULL, 0, NULL, 0 } +}; + +void usage(void) +{ + fprintf(stderr, "usage: gen4asm [-o outputfile] inputfile\n"); +} + +int main(int argc, char **argv) +{ + FILE *output = stdout; + struct brw_program_instruction *entry; + int err; + char o; + + while ((o = getopt_long(argc, argv, "o:", longopts, NULL)) != -1) { + switch (o) { + case 'o': + if (strcmp(optarg, "-") != 0) { + output = fopen(optarg, "w"); + if (output == NULL) { + perror("Couldn't open output file"); + exit(1); + } + } + break; + default: + usage(); + exit(1); + } + } + argc -= optind; + argv += optind; + if (argc != 1) { + usage(); + exit(1); + } + + if (strcmp(argv[0], "-") != 0) { + yyin = fopen(argv[0], "r"); + if (yyin == NULL) { + perror("Couldn't open input file"); + exit(1); + } + } + + err = yyparse(); + + for (entry = compiled_program.first; + entry != NULL; + entry = entry->next) { + fprintf(output, " { 0x%08x, 0x%08x, 0x%08x, 0x%08x },\n", + ((int *)(&entry->instruction))[0], + ((int *)(&entry->instruction))[1], + ((int *)(&entry->instruction))[2], + ((int *)(&entry->instruction))[3]); + } + + return err; +} |