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2013-08-15assembler: error for the wrong syntax of SEND instruction on GEN6+Xiang, Haihao
predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions predicate SEND execsize dst sendleadreg payload imm32reg instoptions predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions The above four syntaxes are only used on legacy platforms which support implied move from payload to dst. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-05-22assembler: Add support for the SENDC instruction.Matt Turner
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Mark format() as PRINTFLIKE in the disassemblerDamien Lespiau
So when making changes in code using that function, we get warnings about mismatches between the format string and arguments. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Fix the decoding of the destination horizontal strideDamien Lespiau
dest_horizontal_stride needs go through the horiz_stride[] indirection to pick up the rigth stride when its value is 11b (4 elements). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Group the header inclusions togetherDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Don't use GL typesDamien Lespiau
sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' assembler/*.[ch] Drop the GL types here, they don't bring anything to the table. For instance, GLuint has no guarantee to be 32 bits, so it does not make too much sense to use it in structure describing hardware tables and opcodes. Of course, some bikeshedding can be applied to use uin32_t instead, I figured that some of the GLuint are used without size constraints, so a sed with uint32_t did not seem the right thing to do. On top of that initial sed, one bothered enough could change the structures with size constraints to actually use uint32_t. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Remove trailing white spaceDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use defines for widthDamien Lespiau
Instead of just using hardcoded numbers or resorting to ffs(). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Merge declared_register's type into the reg structureDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Finish importing brw_eu_*c from mesaDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use set_instruction_src1() in sendDamien Lespiau
No reason not to! Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Put struct opcode_desc back in brw_context.hDamien Lespiau
I originally moved struct opcode_desc from brw_context.h to brw_eu.h on the mesa side, but that was before the realization we needed struct brw_context if we wanted to not touch the code too much. So put it back there now that the mesa patch has been dropped. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Don't pollute the library files with gen4asm.hDamien Lespiau
gen4asm.h is assembler specific while we want the library files to be somewhat of a proper library. This means that we have to redefine the GL* typedefs for brw_structs.h, not using any of thet GL typedef will be for a future commit. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use brw_*() functions for 3-src instructionsDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Add support for D and UD in 3-src instructionsDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Expose setters for 3src operandsDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Introduce set_instruction_saturate()Damien Lespiau
Also simplify the logic that was setting the saturate bit in the math instruction. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Introduce set_intruction_pred_cond()Damien Lespiau
This allow us to factor out the test that checks if, when using both predicates and conditional modifiers, we are using the same flag register. Also get rid of of a FIXME that we are now dealing with (the warning mentioned above). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Introduce set_instruction_opcode()Damien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Isolate all the options in their own structureDamien Lespiau
Like with the predicate fields before, there's no need to use the full instruction to collect the list of options. This allows us to decouple the list of options from a specific instruction encoding. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Unify adding options to the headerDamien Lespiau
Right now we have duplicated code for when the option is the last in the list or not. Put that code in a common function. Interestingly it appears that both sides haven't been kept in sync and that EOT and ACCWRCTRL had limitations on where they had to be in the option list. It's fixed now! Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Gather all predicate data in its own structureDamien Lespiau
Rather than user a full instruction for that. Also use set_instruction_predicate() for a case that coud not be done like that before the refactoring (because everyone now uses the same instruction structure). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Move struct relocation out of relocatable instructionsDamien Lespiau
Now that all instructions (relocatable or not) are struct brw_program_instructions, this means we can move the relocation specific information out the "relocatable instruction" structure. This will allow us to share the relocation information between different types of instructions. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Unify all instructions to be brw_program_instructionsDamien Lespiau
Time to finally unify all instructions on the same structure. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Renamed the instruction field to insnDamien Lespiau
This will be less typing for the refactoring to come (which is use struct brw_program_instruction in gram.y for the type of all the instructions). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use brw_set_src1()Damien Lespiau
Everything is now aligned to be able to use brw_set_src1() in the opcode generation, so use it. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Implement register-indirect addressing mode in brw_set_src1()Damien Lespiau
The assembler allows people to do that and that's something available since Crestline. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Fix ')' placement in conditionDamien Lespiau
A small typo in the condition. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Cleanup visibility of a few global variables/functionsDamien Lespiau
Not everything has to be exported out the compilation unit. Do a small cleanup pass. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Port the warning and error reporting to warn()/error()Damien Lespiau
This way we ensure to have a single place where these are handled. The immediate benefit is that now line numbers are always printed out, which is quite handy. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use brw_set_src0()Damien Lespiau
Unfortunately, it's all a walk in the park. Both, internal code in the assembler and external shaders (libva) generate registers that trigger assertions in brw_eu_emit.c's brw_validate(). To fix all that I took the option to be able to emit warning with the -W flag but still make the assembler generate the same opcodes. We can fix all this, but it requires validation, something that I cannot do right now. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Add the input filename to the error/warning messagesDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Add a check for when ExecSize and width are 1Damien Lespiau
Another check (that we hit if we try to use brw_set_src0()). Again, protect it with the -W option. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Add a check for when width is 1 and hstride is not 0Damien Lespiau
The list of region restrictions in bspec do say that we can't have: width == 1 && hstrize != 0 We do have plenty of assembly code that don't respect that behaviour. So let's hide the warning under a -W flag (for now) while we fix things. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Add error() and warn() shorthands and use them in set_src[01]Damien Lespiau
Now that we have locations, we can write error() and warn() functions giving more information about where it's going wrong. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Add location supportDamien Lespiau
Let's generate location information about the tokens we are parsing. This can be used to give accurate location when reporting errors and warnings. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Don't warn if identical declared registers are redefinedDamien Lespiau
There's no real need to warn when the same register is declared twice. Currently the libva driver does do that and this warning makes other errors really hide in a sea of warnings. Redefining a register with different parameters is a real error though, so we should not allow that and error out in that case. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Store immediate values in reg.dw1.udDamien Lespiau
Another step in pushing the parsing in struct brw_reg. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Fix comparisons between reg.type and Architecture registersDamien Lespiau
Of course the assertion is there to make sure GRF and MRF have a reg.nr < 128. To exclude ARF registers, reg.file has be checked, not reg.type (channel type). Most likely a typo never caught. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: ExecSize can be as big as 32 channelsDamien Lespiau
See the IVB PRM, vol4 part3 5.2.3. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Factor out the source register validationDamien Lespiau
The goal is to use brw_set_src[01](), so let's start by validating the register we have before generating the opcode. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use brw_set_dest() to encode the destinationDamien Lespiau
A few notes: I needed to introduce a brw context and compile structs. These are only used to get which generation we are compiling code for, but eventually we can use more of the infrastructure. brw_set_dest() uses the destination register width to program the instruction execution size. The assembler can either take subnr in bytes or in number of elements, so we need a resolve step when setting a brw_reg. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Factor out the destination register validationDamien Lespiau
The goal is to use brw_set_dest(), so let's start by validating the register we have before generating the opcode. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use brw_reg in the source operandDamien Lespiau
Last refactoring step in transition to struct brw_reg. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Get rid of src operand's swizzle_setDamien Lespiau
swizzle_set can be derived from the value of swizzle itself, no need for that field. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Consolidate the swizzling configuration on 8 bitsDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Replace struct dst_operand by struct brw_regDamien Lespiau
One more step on the road to replacing all register-like structures by struct brw_reg. Two things in this commit are worth noting: * As we are using more and more brw_reg, a lot of the field-by-field assignments can be replaced by 1 assignment which results is a reduction of code * As the destination horizontal stride is now stored on 2 bits in brw_reg, it's not possible to defer the handling of DEFAULT_DSTREGION (aka (int)-1) when setting the destination operand. It has to be done when parsing the region and resolve_dst_region() is a helper for that task. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Unify the direct and indirect register typeDamien Lespiau
They are all struct brw_reg registers now. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Replace struct indirect_reg by struct brw_regDamien Lespiau
More code simplification can be layered on top of that (by using some brw_* helpers to create registers), that'd be for another commit. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Replace struct direct_reg by struct brw_regDamien Lespiau
More code simplification can be layered on top of that (by using some brw_* helpers to create registers), that'd be for another commit. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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