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There is no guarantee that spinners are and will be implemented
using batches. As we have igt_spin_t, manipulate it through
igt_spin_* functions consistently and hide the batch nature.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Instead of opencoding the poll into the spinner, use
a helper to check if spinner has started.
v2: use zero as presumed offset (Chris)
v3: cleanup the relocs (Chris)
v4: leave the domains to zero, avoid relocation (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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This patch is a change to igt file tests/i915/gem_ctx_isolation.c to
add and enable Gen11 support.
This patch accounts for whitelisted registers appropriately for the
different Gen levels.
This patch accounts for the changed MMIO offsets of Gen11.
This patch redefines MAX_REG from 0x40000 to 0x200000 due to the
larger total register space for Gen11 mmio offsets.
A current Gen11 SKU has two video engines (with indexes 0 and 2,
for VCS0 and VCS2), with VCS1 not being used.
Current kernel and igt limitations only allow for VCS0 and VCS1.
Those limitations are in the process of being removed. See for
example the RFC/PATCH series on igt-dev from Andy Shyti:
[igt-dev] [RFC PATCH v9 0/5] new engine discovery interface
which depends on in-process kernel "media scalability" patches.
Lacking the above infrastructure at the moment:
The array of registers to be tested includes VCS2 and VCS3 registers.
They are present as a provision for the future, but they will
not actually be tested as those engines are not yet known to the
underlying infrastructure.
When run on Gen11 this patch skips the sub-tests for the non-existent VCS1
with these warnings:
Test requirement not met in function gem_require_engine, file ../lib/igt_gt.h:114:
Test requirement: gem_has_engine(gem_fd, class, instance)
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Verify that our list of nonpriv registers exist and are writable.
v2: TD_CTL has a write_mask of 0xffff instead of being a masked
register.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Dale B Stimson <dale.b.stimson@intel.com>
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On Skylake, BB_OFFSET seems to be unstable. Since this is an
offset into the batch at the time of CS execution, it should be actively
written to as we read from the register so allow it a qword of
discrepancy (since the CS should be reading in qwords). This still
allows us to detect dirt across the rest of the register field, should
that be required.
v2: restrict ignore_bits to only BIT(2) that we see fluctuate in testing
(Antonio)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
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We can already move all the tests with distinct prefixes: gem_, gen3_
and i915_.
pm_ and drv_ tests will follow in batches, so we can do the
adjustments in the reporting/filtering layer of the CI system.
v2: Fix test-list.txt generation with meson
v3: Fix docs build (Petri)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Tested-by: Petri Latvala <petri.latvala@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
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