1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
|
/*
* Copyright © 2014 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Arun Siluvery <arun.siluvery@linux.intel.com>
*
*/
#define _GNU_SOURCE
#include "igt.h"
#include <fcntl.h>
enum operation {
GPU_RESET,
SUSPEND_RESUME,
SIMPLE_READ,
};
struct intel_wa_reg {
uint32_t addr;
uint32_t value;
uint32_t mask;
};
static struct intel_wa_reg *wa_regs;
static int num_wa_regs;
static void wait_gpu(void)
{
int fd = drm_open_driver(DRIVER_INTEL);
gem_quiescent_gpu(fd);
close(fd);
}
static void test_hang_gpu(void)
{
int fd = drm_open_driver(DRIVER_INTEL);
igt_post_hang_ring(fd, igt_hang_ring(fd, I915_EXEC_DEFAULT));
close(fd);
}
static void test_suspend_resume(void)
{
igt_info("Suspending the device ...\n");
igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_NONE);
}
static int workaround_fail_count(void)
{
int i, fail_count = 0;
/* There is a small delay after coming ot of rc6 to the correct
render context values will get loaded by hardware (bdw,chv).
This here ensures that we have the correct context loaded before
we start to read values */
wait_gpu();
igt_debug("Address\tval\t\tmask\t\tread\t\tresult\n");
for (i = 0; i < num_wa_regs; ++i) {
const uint32_t val = intel_register_read(wa_regs[i].addr);
const bool ok = (wa_regs[i].value & wa_regs[i].mask) ==
(val & wa_regs[i].mask);
igt_debug("0x%05X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
val, ok ? "OK" : "FAIL");
if (!ok) {
igt_warn("0x%05X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
wa_regs[i].addr, wa_regs[i].value,
wa_regs[i].mask,
val, ok ? "OK" : "FAIL");
fail_count++;
}
}
return fail_count;
}
static void check_workarounds(enum operation op)
{
igt_assert_eq(workaround_fail_count(), 0);
switch (op) {
case GPU_RESET:
test_hang_gpu();
break;
case SUSPEND_RESUME:
test_suspend_resume();
break;
case SIMPLE_READ:
return;
default:
igt_assert(0);
}
igt_assert_eq(workaround_fail_count(), 0);
}
igt_main
{
igt_fixture {
int device = drm_open_driver_master(DRIVER_INTEL);
const int gen = intel_gen(intel_get_drm_devid(device));
struct pci_device *pci_dev;
FILE *file;
char *line = NULL;
size_t line_size;
int i, fd;
igt_require_gem(device);
pci_dev = intel_get_pci_device();
igt_require(pci_dev);
intel_register_access_init(pci_dev, 0, device);
fd = igt_debugfs_open(device, "i915_wa_registers", O_RDONLY);
file = fdopen(fd, "r");
igt_assert(getline(&line, &line_size, file) > 0);
igt_debug("i915_wa_registers: %s", line);
sscanf(line, "Workarounds applied: %d", &num_wa_regs);
/* For newer gens, the lri wa list has always something.
* If it doesn't, go and add one. */
if (gen >= 8)
igt_assert_lt(0, num_wa_regs);
else
igt_assert_lte(0, num_wa_regs);
wa_regs = malloc(num_wa_regs * sizeof(*wa_regs));
igt_assert(wa_regs);
i = 0;
while (getline(&line, &line_size, file) > 0) {
igt_debug("%s", line);
if (sscanf(line, "0x%X: 0x%08X, mask: 0x%08X",
&wa_regs[i].addr,
&wa_regs[i].value,
&wa_regs[i].mask) == 3)
i++;
}
igt_assert_lte(i, num_wa_regs);
free(line);
fclose(file);
close(fd);
close(device);
}
igt_subtest("basic-read")
check_workarounds(SIMPLE_READ);
igt_subtest("reset")
check_workarounds(GPU_RESET);
igt_subtest("suspend-resume")
check_workarounds(SUSPEND_RESUME);
igt_fixture {
free(wa_regs);
intel_register_access_fini();
}
}
|
