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authorJanakarajan Natarajan <Janakarajan.Natarajan@amd.com>2018-11-07 20:59:07 +0000
committerBorislav Petkov <bp@suse.de>2018-11-07 22:21:03 +0100
commit08e823c2c5899ef2de3aa1727233f1f19e8c1cc1 (patch)
tree9fc0073dea3de144a8a3ffd8b0ab1c328e2db784
parent43500e6f294d175602606c77bfb0d8cd4ea88b4f (diff)
x86/cpufeatures: Add WBNOINVD feature definition
Add a new cpufeature definition for the WBNOINVD instruction. The WBNOINVD instruction writes all modified cache lines in all levels of the cache associated with a processor to main memory while retaining the cached values. Both AMD and Intel support this instruction. Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> CC: David Woodhouse <dwmw@amazon.co.uk> CC: Fenghua Yu <fenghua.yu@intel.com> CC: "H. Peter Anvin" <hpa@zytor.com> CC: Ingo Molnar <mingo@redhat.com> CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> CC: Rudolf Marek <r.marek@assembler.cz> CC: Thomas Gleixner <tglx@linutronix.de> CC: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/1541624211-32196-1-git-send-email-Janakarajan.Natarajan@amd.com
-rw-r--r--arch/x86/include/asm/cpufeatures.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 28c4a502b419..39a48f06d39d 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -281,6 +281,7 @@
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
+#define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */
#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */