diff options
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-31 18:12:52 -0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-11-11 23:51:26 +0100 |
| commit | 223a6fdfbf7e26d9ad5ee54e258eb164412fcbc0 (patch) | |
| tree | 8c82d57803ca8db0db142869f1152663d8b5c232 | |
| parent | 8a52fd9f240a6e2b73361fb825145f9951fc552d (diff) | |
drm/i915: implement timing override workarounds on LPT
These workarounds are documented on the CRT mode set sequence.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1b57fbc5eb5b..7509e7903c22 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1729,6 +1729,11 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, assert_fdi_tx_enabled(dev_priv, cpu_transcoder); assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); + /* Workaround: set timing override bit. */ + val = I915_READ(_TRANSA_CHICKEN2); + val |= TRANS_AUTOTRAIN_GEN_STALL_DIS; + I915_WRITE(_TRANSA_CHICKEN2, val); + val = TRANS_ENABLE; pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); @@ -1780,6 +1785,11 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv, /* wait for PCH transcoder off, transcoder state */ if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50)) DRM_ERROR("Failed to disable PCH transcoder\n"); + + /* Workaround: clear timing override bit. */ + val = I915_READ(_TRANSA_CHICKEN2); + val &= ~TRANS_AUTOTRAIN_GEN_STALL_DIS; + I915_WRITE(_TRANSA_CHICKEN2, val); } /** |