diff options
author | Andrzej Hajda <a.hajda@samsung.com> | 2016-10-05 12:03:09 +0200 |
---|---|---|
committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:53:46 +0900 |
commit | 5bd05638ae648ea19b57cd0b658009c2fc4dfcef (patch) | |
tree | 3c0d8b93c4fcbd26a0247da4c3750f4a7176aa3c | |
parent | bb1128f4ca63fbf4f3e9a1b316ad7322228fe4c6 (diff) |
drm/exynos/dsi: mimic indentation of mainline driver
This patch synchronizes indentation from mainline driver.
It helps in developing dsi driver in both branches.
Change-Id: I3ad3704d0cf9d58a4021cbc8c52ec4201a5f5724
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_dsi.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 97aea8efb8bd..599c249a544f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -209,7 +209,7 @@ #define DSI_XFER_TIMEOUT_MS 100 #define DSI_RX_FIFO_EMPTY 0x30800002 -#define OLD_SCLK_MIPI_CLK_NAME "pll_clk" +#define OLD_SCLK_MIPI_CLK_NAME "pll_clk" static char *clk_names[5] = { "bus_clk", "sclk_mipi", "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", @@ -745,8 +745,10 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after * the last payload clock bit of a HS transmission burst */ - reg = reg_values[PHYTIMING_CLK_PREPARE] | reg_values[PHYTIMING_CLK_ZERO] | - reg_values[PHYTIMING_CLK_POST] | reg_values[PHYTIMING_CLK_TRAIL]; + reg = reg_values[PHYTIMING_CLK_PREPARE] | + reg_values[PHYTIMING_CLK_ZERO] | + reg_values[PHYTIMING_CLK_POST] | + reg_values[PHYTIMING_CLK_TRAIL]; exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); @@ -1888,7 +1890,7 @@ static int exynos_dsi_probe(struct platform_device *pdev) } dev_info(dev, "failed to get the clock: %s\n", - clk_names[i]); + clk_names[i]); return PTR_ERR(dsi->clks[i]); } } |