diff options
| author | Keith Busch <keith.busch@intel.com> | 2017-04-28 12:02:49 -0400 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-05-22 18:42:44 -0500 |
| commit | 69a3025def543b66a9610c86706eebb6b160d3b8 (patch) | |
| tree | e621e68777b6ef6e7209a245d746ce6838dcac24 | |
| parent | 993d668183fa49b63939a4f62a558d487fd50c22 (diff) | |
PCI/DPC: Fix control register setting
This driver was OR'ing desired bits from the existing control setting.
That could create an invalid DPC Trigger Enabled configuration if the
platform previously set this to "ERR_FATAL", 01b. The driver currently
wants to set this to ERR_NONFATAL/ERR_FATAL, 10b, and the logical OR of
this gets 11b, which is reserved. Fix that by masking off the fields it is
setting.
Signed-off-by: Keith Busch <keith.busch@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| -rw-r--r-- | drivers/pci/pcie/pcie-dpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/pcie/pcie-dpc.c b/drivers/pci/pcie/pcie-dpc.c index 0bf084357237..c39f32e42b4d 100644 --- a/drivers/pci/pcie/pcie-dpc.c +++ b/drivers/pci/pcie/pcie-dpc.c @@ -144,7 +144,7 @@ static int dpc_probe(struct pcie_device *dev) dpc->rp = (cap & PCI_EXP_DPC_CAP_RP_EXT); - ctl |= PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN; + ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN; pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl); dev_info(&dev->device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", |