diff options
| author | Suman Anna <s-anna@ti.com> | 2020-08-25 12:21:45 -0500 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2020-08-31 06:31:23 -0500 |
| commit | 67cfbb62132e4210b4c4785b0ca1fbe4cafb7c4d (patch) | |
| tree | 9925ec8a9ba16099314f969759330991d24de686 /arch/arm64/boot/dts/ti | |
| parent | 1939d37f94937cf5082ee2612b76106cb3d90978 (diff) | |
arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores
Add a reserved memory node to reserve a portion of the DDR memory to be
used for performing inter-processor communication between all the remote
processors running RTOS on the TI J721E EVM boards. 28 MB of memory is
reserved for this purpose, and this accounts for all the vrings and vring
buffers between all the possible pairs of remote processors.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-9-s-anna@ti.com
Diffstat (limited to 'arch/arm64/boot/dts/ti')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 0e28be492ac2..d69d90c8b5e3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -61,6 +61,12 @@ reg = <0x00 0xa8100000 0x00 0xf00000>; no-map; }; + + rtos_ipc_memory_region: ipc-memories@aa000000 { + reg = <0x00 0xaa000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; }; }; |