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authorBeata Michalska <beata.michalska@arm.com>2021-06-03 15:06:27 +0100
committerPeter Zijlstra <peterz@infradead.org>2021-06-24 09:07:51 +0200
commitadf3c31e18b765ea24eba7b0c1efc076b8ee3d55 (patch)
tree097810c605920c329f9549d0dc595b2e46f67b85 /arch/hexagon
parentc744dc4ab58d1c09624ca3397cf15b142a0e0cb7 (diff)
sched/doc: Update the CPU capacity asymmetry bits
Update the documentation bits referring to capacity aware scheduling with regards to newly introduced SD_ASYM_CPUCAPACITY_FULL sched_domain flag. Signed-off-by: Beata Michalska <beata.michalska@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Valentin Schneider <valentin.schneider@arm.com> Reviewed-by: Dietmar Eggemann <dietmar.eggemann@arm.com> Link: https://lore.kernel.org/r/20210603140627.8409-4-beata.michalska@arm.com
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