diff options
| author | Len Brown <len.brown@intel.com> | 2014-02-04 23:56:40 -0500 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2014-08-15 17:06:40 -0400 |
| commit | a138b56800f4b83a7af69a9958d04f0f124eb37b (patch) | |
| tree | 1626c54b0acadbefbb5d3d391503844a2fbb5218 /arch/ia64/sn/kernel/pio_phys.S | |
| parent | 8c058d53f6f2eb0b9cd3bc4ce5c053a64dded671 (diff) | |
intel_idle: Broadwell support
Broadwell (BDW) is similar to Haswell (HSW), the preceding processor generation.
Currently, the only difference in their C-state tables is that PC3 max exit latency
is 33usec on HSW and 40usec on BDW.
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/ia64/sn/kernel/pio_phys.S')
0 files changed, 0 insertions, 0 deletions