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| author | Thomas Gleixner <tglx@linutronix.de> | 2018-05-02 16:11:12 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-05-02 16:11:12 +0200 |
| commit | 604a98f1df2897f9ea6ca6bdab8e1c2d6844be01 (patch) | |
| tree | 99471700986d14cd5cace3e535dfcbd0e07464cb /arch/mips/lib/memset.S | |
| parent | 1cfd904f16740df21b2df7b41c7a0dc00cbd434c (diff) | |
| parent | 7dba33c6346c337aac3f7cd188137d4a6d3d1f3a (diff) | |
Merge branch 'timers/urgent' into timers/core
Pick up urgent fixes to apply dependent cleanup patch
Diffstat (limited to 'arch/mips/lib/memset.S')
| -rw-r--r-- | arch/mips/lib/memset.S | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S index a1456664d6c2..f7327979a8f8 100644 --- a/arch/mips/lib/memset.S +++ b/arch/mips/lib/memset.S @@ -219,7 +219,7 @@ 1: PTR_ADDIU a0, 1 /* fill bytewise */ R10KCBARRIER(0(ra)) bne t1, a0, 1b - sb a1, -1(a0) + EX(sb, a1, -1(a0), .Lsmall_fixup\@) 2: jr ra /* done */ move a2, zero @@ -252,13 +252,18 @@ PTR_L t0, TI_TASK($28) andi a2, STORMASK LONG_L t0, THREAD_BUADDR(t0) - LONG_ADDU a2, t1 + LONG_ADDU a2, a0 jr ra LONG_SUBU a2, t0 .Llast_fixup\@: jr ra - andi v1, a2, STORMASK + nop + +.Lsmall_fixup\@: + PTR_SUBU a2, t1, a0 + jr ra + PTR_ADDIU a2, 1 .endm |