diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-06-03 14:01:43 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-06-03 14:01:43 -0700 |
commit | f66e797b407bc03a438d1f05057dc7918bab473f (patch) | |
tree | 17cebbf1f6ff43f62d414cd1b57d1f82bb9daf56 /arch/riscv/include/asm/alternative-macros.h | |
parent | 4ab6cfc4ad9f867a107b0ef029088dd4c0a8f83c (diff) | |
parent | 61114e734ccb804bc12561ab4020745e02c468c2 (diff) |
Merge tag 'riscv-for-linus-5.19-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Palmer Dabbelt:
"This is mostly some DT updates, but also a handful of cleanups and
some fixes. The most user-visible of those are:
- A device tree for the Sundance Polarberry, along with a handful of
fixes and clenups to the PolarFire SOC device trees and bindings.
- The memfd_secret syscall number is now visible to userspace,
- Some improvements to the vm layout dump, which really should have
followed shortly after the sv48 patches but I missed"
* tag 'riscv-for-linus-5.19-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Move alternative length validation into subsection
riscv: mm: init: make pt_ops_set_[early|late|fixmap] static
riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild
RISC-V: Mark IORESOURCE_EXCLUSIVE for reserved mem instead of IORESOURCE_BUSY
riscv: Wire up memfd_secret in UAPI header
riscv: Fix irq_work when SMP is disabled
riscv: Improve virtual kernel memory layout dump
riscv: Initialize thread pointer before calling C functions
Documentation: riscv: Add sv48 description to VM layout
RISC-V: Only default to spinwait on SBI-0.1 and M-mode
riscv: dts: icicle: sort nodes alphabetically
riscv: microchip: icicle: readability fixes
riscv: dts: microchip: add the sundance polarberry
dt-bindings: riscv: microchip: add polarberry compatible string
dt-bindings: vendor-prefixes: add Sundance DSP
riscv: dts: microchip: make the fabric dtsi board specific
dt-bindings: riscv: microchip: document icicle reference design
riscv: dts: microchip: remove soc vendor from filenames
riscv: dts: microchip: move sysctrlr out of soc bus
riscv: dts: microchip: remove icicle memory clocks
Diffstat (limited to 'arch/riscv/include/asm/alternative-macros.h')
-rw-r--r-- | arch/riscv/include/asm/alternative-macros.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index e13b1f6bb400..ec2f3f1b836f 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -27,9 +27,9 @@ \new_c .option pop 889 : - .previous .org . - (889b - 888b) + (887b - 886b) .org . - (887b - 886b) + (889b - 888b) + .previous .endif .endm @@ -94,9 +94,9 @@ new_c "\n" \ ".option pop\n" \ "889 :\n" \ - ".previous\n" \ ".org . - (887b - 886b) + (889b - 888b)\n" \ ".org . - (889b - 888b) + (887b - 886b)\n" \ + ".previous\n" \ ".endif\n" #define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \ |