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authorThomas Betker <thomas.betker@rohde-schwarz.com>2015-05-12 08:22:01 +0200
committerMichal Simek <michal.simek@xilinx.com>2015-07-22 09:37:58 +0200
commit6632d4fdd790965a2e4741a3652a1c365d52ae2e (patch)
tree1da0fde0cb98f9d5c3e8f3a5918b4d871a87aff1 /arch/s390/hypfs
parent974a2aba99d29bada9212134e7565d2364967636 (diff)
ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1)
This patch is based on the commit 1a8e41cd672f ("ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register") Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. For Zynq, this fix avoids memory inconsistencies between Gigabit Ethernet controller (GEM) and CPU when DMA_CMA is disabled. Suggested-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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