diff options
author | Jeff Garzik <jeff@garzik.org> | 2006-06-13 20:29:04 -0400 |
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committer | Jeff Garzik <jeff@garzik.org> | 2006-06-13 20:29:04 -0400 |
commit | b5ed7639c9f502898af4109e778f5613dacbfd9c (patch) | |
tree | abe908c60ce1ea8f201028c9fc830cacd25c724b /arch/sparc/kernel/smp.c | |
parent | 0638dec01e89059c853515ab71c55fd13ba5a8ea (diff) | |
parent | eb35cf60e462491249166182e3e755d3d5d91a28 (diff) |
Merge branch 'master' into upstream
Diffstat (limited to 'arch/sparc/kernel/smp.c')
-rw-r--r-- | arch/sparc/kernel/smp.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/sparc/kernel/smp.c b/arch/sparc/kernel/smp.c index a93f5da6855d..40b42c88e6a7 100644 --- a/arch/sparc/kernel/smp.c +++ b/arch/sparc/kernel/smp.c @@ -69,6 +69,17 @@ void __init smp_store_cpu_info(int id) "clock-frequency", 0); cpu_data(id).prom_node = cpu_node; cpu_data(id).mid = cpu_get_hwmid(cpu_node); + + /* this is required to tune the scheduler correctly */ + /* is it possible to have CPUs with different cache sizes? */ + if (id == boot_cpu_id) { + int cache_line,cache_nlines; + cache_line = 0x20; + cache_line = prom_getintdefault(cpu_node, "ecache-line-size", cache_line); + cache_nlines = 0x8000; + cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines); + max_cache_size = cache_line * cache_nlines; + } if (cpu_data(id).mid < 0) panic("No MID found for CPU%d at node 0x%08d", id, cpu_node); } |