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authorLinus Torvalds <torvalds@linux-foundation.org>2016-05-16 14:24:51 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2016-05-16 14:24:51 -0700
commitcf6ed9a6682d3f171cf9550d4bbe0ef31b768a7e (patch)
tree53afc898db61ca45404c5796e54e35ae200bbfa9 /arch/x86/kernel/cpu/common.c
parent36db171cc733bc7b8c628ef21831467d1919decd (diff)
parent754a92305980b1fecffe033dd3fdc49c37f8e4b0 (diff)
Merge branch 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull RAS updates from Ingo Molnar: "Main changes in this cycle were: - AMD MCE/RAS handling updates (Yazen Ghannam, Aravind Gopalakrishnan) - Cleanups (Borislav Petkov) - logging fix (Tony Luck)" * 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/RAS: Add SMCA support to AMD Error Injector EDAC, mce_amd: Detect SMCA using X86_FEATURE_SMCA x86/mce: Update AMD mcheck init to use cpu_has() facilities x86/cpu: Add detection of AMD RAS Capabilities x86/mce/AMD: Save an indentation level in prepare_threshold_block() x86/mce/AMD: Disable LogDeferredInMcaStat for SMCA systems x86/mce/AMD: Log Deferred Errors using SMCA MCA_DE{STAT,ADDR} registers x86/mce: Detect local MCEs properly x86/mce: Look in genpool instead of mcelog for pending error records x86/mce: Detect and use SMCA-specific msr_ops x86/mce: Define vendor-specific MSR accessors x86/mce: Carve out writes to MCx_STATUS and MCx_CTL x86/mce: Grade uncorrected errors for SMCA-enabled systems x86/mce: Log MCEs after a warm rest on AMD, Fam17h and later x86/mce: Remove explicit smp_rmb() when starting CPUs sync x86/RAS: Rename AMD MCE injector config item
Diffstat (limited to 'arch/x86/kernel/cpu/common.c')
-rw-r--r--arch/x86/kernel/cpu/common.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 8394b3d1f94f..dbc6f066e231 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -717,6 +717,13 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
}
}
+ if (c->extended_cpuid_level >= 0x80000007) {
+ cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
+
+ c->x86_capability[CPUID_8000_0007_EBX] = ebx;
+ c->x86_power = edx;
+ }
+
if (c->extended_cpuid_level >= 0x80000008) {
cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
@@ -729,9 +736,6 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
c->x86_phys_bits = 36;
#endif
- if (c->extended_cpuid_level >= 0x80000007)
- c->x86_power = cpuid_edx(0x80000007);
-
if (c->extended_cpuid_level >= 0x8000000a)
c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);