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| author | Simon Guo <wei.guo.simon@gmail.com> | 2018-05-23 15:01:59 +0800 |
|---|---|---|
| committer | Paul Mackerras <paulus@ozlabs.org> | 2018-06-01 10:30:00 +1000 |
| commit | 13989b65ebb74c05c577dbbcc111e1fdd7da763a (patch) | |
| tree | 5430a76d199a1bde726f9de6849a1000e88474b9 /drivers/fpga/fpga-mgr.c | |
| parent | 8d2e2fc5e082a7b3f858cefb6e65700f28d2955e (diff) | |
KVM: PPC: Book3S PR: Add math support for PR KVM HTM
The math registers will be saved into vcpu->arch.fp/vr and corresponding
vcpu->arch.fp_tm/vr_tm area.
We flush or giveup the math regs into vcpu->arch.fp/vr before saving
transaction. After transaction is restored, the math regs will be loaded
back into regs.
If there is a FP/VEC/VSX unavailable exception during transaction active
state, the math checkpoint content might be incorrect and we need to do
treclaim./load the correct checkpoint val/trechkpt. sequence to retry the
transaction. That will make our solution complicated. To solve this issue,
we always make the hardware guest MSR math bits (shadow_msr) consistent
with the MSR val which guest sees (kvmppc_get_msr()) when guest msr is
with tm enabled. Then all FP/VEC/VSX unavailable exception can be delivered
to guest and guest handles the exception by itself.
Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Diffstat (limited to 'drivers/fpga/fpga-mgr.c')
0 files changed, 0 insertions, 0 deletions