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authorAya Levin <ayal@nvidia.com>2020-11-20 15:03:32 -0800
committerSaeed Mahameed <saeedm@nvidia.com>2020-11-26 18:43:48 -0800
commit21adf05d4584c99a07a604224b9cfeddcc6bc47c (patch)
tree0653a9b0387844f7654ef640290e5b87e3b7d8bd /drivers/fpga/zynq-fpga.c
parent349125ba232ea53d71a57c65c81f109c323cc369 (diff)
net/mlx5: Expose IP-in-IP TX and RX capability bits
Expose FW indication that it supports stateless offloads for IP over IP tunneled packets per direction. In some HW like ConnectX-4 IP-in-IP support is not symmetric, it supports steering on the inner header but it doesn't TX-Checksum and TSO. Add IP-in-IP capability per direction to cover this case as well. Note: only if both indications are turned on, the global tunnel_stateless_ip_over_ip is on too. Signed-off-by: Aya Levin <ayal@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/fpga/zynq-fpga.c')
0 files changed, 0 insertions, 0 deletions