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authorJason Gunthorpe <jgg@nvidia.com>2021-01-19 10:55:19 -0400
committerJason Gunthorpe <jgg@nvidia.com>2021-01-19 10:55:19 -0400
commit02487bcc84cdec676b667096f896ba8ad254aae9 (patch)
treedf66e03b2c63f3488326357882f84b16ed532e1b /drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
parenta6dc16b6996388d016df83fb92eae16242ab7ac5 (diff)
parent1368ead04c361bb4595ace9122c79dd75e54a650 (diff)
Merge branch 'devx_set_get' into rdma.git for-next
Leon Romanovsky says: ==================== Be more strict with DEVX get/set operations for the obj_id. ==================== Based on the mlx5-next branch at git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux due to dependencies. * branch 'devx_set_get': RDMA/mlx5: Use strict get/set operations for obj_id RDMA/mlx5: Use the correct obj_id upon DEVX TIR creation net/mlx5: Expose ifc bits for query modify header
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 1dd040166c63..19d9aa76cfbf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -30,6 +30,7 @@
#define EEPROM_I2C_TARGET_ADDR_VEGA20 0xA0
#define EEPROM_I2C_TARGET_ADDR_ARCTURUS 0xA8
#define EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342 0xA0
+#define EEPROM_I2C_TARGET_ADDR_SIENNA_CICHLID 0xA0
/*
* The 2 macros bellow represent the actual size in bytes that
@@ -62,7 +63,8 @@
static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
{
if ((adev->asic_type == CHIP_VEGA20) ||
- (adev->asic_type == CHIP_ARCTURUS))
+ (adev->asic_type == CHIP_ARCTURUS) ||
+ (adev->asic_type == CHIP_SIENNA_CICHLID))
return true;
return false;
@@ -100,6 +102,10 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
case CHIP_ARCTURUS:
return __get_eeprom_i2c_addr_arct(adev, i2c_addr);
+ case CHIP_SIENNA_CICHLID:
+ *i2c_addr = EEPROM_I2C_TARGET_ADDR_SIENNA_CICHLID;
+ break;
+
default:
return false;
}