Merge branch 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux into drm-next

- Continued cleanup and restructuring of powerplay
- Fetch VRAM type from vbios rather than hardcoding for SOC15 asics
- Allow ttm to drop its backing store when drivers don't need it
- DC bandwidth calc updates
- Enable DC backlight control pre-DCE11 asics
- Enable DC on all supported asics
- DC Fixes for planes due to the way our hw is ordered vs what drm expects
- DC CTM/regamma fixes
- Misc cleanup and bug fixes

* 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: (89 commits)
  amdgpu/dm: Default PRE_VEGA ASIC support to 'y'
  drm/amd/pp: Remove the cgs wrapper for notify smu version on APU
  drm/amd/display: fix dereferencing possible ERR_PTR()
  drm/amd/display: Refine disable VGA
  drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel
  drm/radeon: Don't turn off DP sink when disconnected
  drm/amd/pp: Rename file name cz_* to smu8_*
  drm/amd/pp: Replace function/struct name cz_* with smu8_*
  drm/amd/pp: Remove unneeded void * casts in cz_hwmgr.c/cz_smumgr.c
  drm/amd/pp: Mv cz uvd/vce pg/dpm functions to cz_hwmgr.c
  drm/amd/pp: Remove dead header file pp_asicblocks.h
  drm/amd/pp: Delete dead code on cz_clockpowergating.c
  drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c
  drm/amdgpu: Remove wrapper layer of smu ip functions
  drm/amdgpu: Don't compared ip_block_type with ip_block_index
  drm/amdgpu: Plus NULL function pointer check
  drm/amd/pp: Move helper functions to smu_help.c
  drm/amd/pp: Replace rv_* with smu10_*
  drm/amd/pp: Fix function parameter not correct
  drm/amd/pp: Add rv_copy_table_from/to_smc to smu backend function table
  ...

1 files changed, 8 insertions, 10 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 215743df0957..9448c45d1b60 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -31,8 +31,6 @@
 #include "sdma0/sdma0_4_0_sh_mask.h"
 #include "sdma1/sdma1_4_0_offset.h"
 #include "sdma1/sdma1_4_0_sh_mask.h"
-#include "mmhub/mmhub_1_0_offset.h"
-#include "mmhub/mmhub_1_0_sh_mask.h"
 #include "hdp/hdp_4_0_offset.h"
 #include "sdma0/sdma0_4_1_default.h"
 
@@ -1172,13 +1170,13 @@ static int sdma_v4_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	/* SDMA trap event */
-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224,
+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 224,
 			      &adev->sdma.trap_irq);
 	if (r)
 		return r;
 
 	/* SDMA trap event */
-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224,
+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 224,
 			      &adev->sdma.trap_irq);
 	if (r)
 		return r;
@@ -1333,7 +1331,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
 {
 	DRM_DEBUG("IH: SDMA trap\n");
 	switch (entry->client_id) {
-	case AMDGPU_IH_CLIENTID_SDMA0:
+	case SOC15_IH_CLIENTID_SDMA0:
 		switch (entry->ring_id) {
 		case 0:
 			amdgpu_fence_process(&adev->sdma.instance[0].ring);
@@ -1349,7 +1347,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
 			break;
 		}
 		break;
-	case AMDGPU_IH_CLIENTID_SDMA1:
+	case SOC15_IH_CLIENTID_SDMA1:
 		switch (entry->ring_id) {
 		case 0:
 			amdgpu_fence_process(&adev->sdma.instance[1].ring);
@@ -1399,7 +1397,7 @@ static void sdma_v4_0_update_medium_grain_clock_gating(
 		if (def != data)
 			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
 
-		if (adev->asic_type == CHIP_VEGA10) {
+		if (adev->sdma.num_instances > 1) {
 			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
 			data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
 				  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
@@ -1427,7 +1425,7 @@ static void sdma_v4_0_update_medium_grain_clock_gating(
 		if (def != data)
 			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
 
-		if (adev->asic_type == CHIP_VEGA10) {
+		if (adev->sdma.num_instances > 1) {
 			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
 			data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
 				 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
@@ -1458,7 +1456,7 @@ static void sdma_v4_0_update_medium_grain_light_sleep(
 			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 
 		/* 1-not override: enable sdma1 mem light sleep */
-		if (adev->asic_type == CHIP_VEGA10) {
+		if (adev->sdma.num_instances > 1) {
 			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
 			data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
 			if (def != data)
@@ -1472,7 +1470,7 @@ static void sdma_v4_0_update_medium_grain_light_sleep(
 			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 
 		/* 0-override:disable sdma1 mem light sleep */
-		if (adev->asic_type == CHIP_VEGA10) {
+		if (adev->sdma.num_instances > 1) {
 			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
 			data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
 			if (def != data)