diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2021-04-13 12:25:16 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2021-04-13 12:25:17 +0200 |
| commit | cd951b3971cdc1f8c76b075f2c97ff357bf141e2 (patch) | |
| tree | 0af9a1eeba0011d2dffc360087808c4c0b7fee54 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | |
| parent | c103b850721e4a79ff9578f131888129c37a4679 (diff) | |
| parent | cbb8f989d5a07cb3e39e9c149a6f89d6c83432aa (diff) | |
Merge tag 'amd-drm-next-5.13-2021-04-12' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.13-2021-04-12:
amdgpu:
- Re-enable GPU reset on VanGogh
- Enable DPM flags for SMART_SUSPEND and MAY_SKIP_RESUME
- Disentangle HG from vga_switcheroo
- S0ix fixes
- W=1 fixes
- Resource iterator fixes
- DMCUB updates
- UBSAN fixes
- More PM API cleanup
- Aldebaran updates
- Modifier fixes
- Enable VCN load balancing with asymmetric engines
- Rework BO structs
- Aldebaran reset support
- Initial LTTPR display work
- Display MALL fixes
- Fall back to YCbCr420 when YCbCr444 fails
- SR-IOV fixes
- RAS updates
- Misc cleanups and fixes
radeon:
- Typo fixes
- Fix error handling for firmware on r6xx
- Fix a missing check in DP MST handling
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210412220732.3845-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 8f98d44490aa..018943113025 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -66,6 +66,7 @@ struct dc_plane_state; struct common_irq_params { struct amdgpu_device *adev; enum dc_irq_source irq_src; + atomic64_t previous_timestamp; }; /** @@ -339,6 +340,15 @@ struct amdgpu_display_manager { struct common_irq_params vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; + /** + * @dmub_trace_params: + * + * DMUB trace event IRQ parameters, passed to registered handlers when + * triggered. + */ + struct common_irq_params + dmub_trace_params[1]; + spinlock_t irq_handler_list_table_lock; struct backlight_device *backlight_dev; @@ -385,6 +395,11 @@ struct amdgpu_display_manager { #endif #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + /** + * @crc_rd_wrk: + * + * Work to be executed in a separate thread to communicate with PSP. + */ struct crc_rd_work *crc_rd_wrk; #endif |