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authorIlya Bakoulin <Ilya.Bakoulin@amd.com>2019-03-28 14:43:29 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-06-22 09:34:09 -0500
commit8e27a2d4cd76095c80dbbf63548175659d4b9d76 (patch)
treed7ef5c0d536ba6ed87877d95775da7cdda2147dd /drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
parent0213541d4b6b241a83611dd8324af024f87b5368 (diff)
drm/amd/display: Fix DCFCLK and SOCCLK not set
[Why] If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML calculations, which ended up causing an assert. [How] Initialize dcfclk_mhz and socclk_mhz values according to the voltage level. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/inc/mod_shared.h')
0 files changed, 0 insertions, 0 deletions