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| author | Xin Ji <xji@analogixsemi.com> | 2021-11-04 11:34:44 +0800 |
|---|---|---|
| committer | Robert Foss <robert.foss@linaro.org> | 2021-11-04 11:13:56 +0100 |
| commit | a43661e7e819b100e1f833a35018560a1d9abb39 (patch) | |
| tree | 572174e1d338a8302c1c94cc18bdd50a476e1759 /drivers/gpu/drm/bridge | |
| parent | 16e101051f329f5f3f2dd810f3687d166580aa3a (diff) | |
dt-bindings:drm/bridge:anx7625:add vendor define
Add 'bus-type' and 'data-lanes' define for port0. Add DP tx lane0,
lane1 swing register setting array, and audio enable flag.
The device which cannot pass DP tx PHY CTS caused by long PCB trace or
embedded MUX, adjusting ANX7625 PHY parameters can pass the CTS test. The
adjusting type include Pre-emphasis, Vp-p, Rterm(Resistor Termination)
and Rsel(Driven Strength). Each lane has maximum 20 registers for
these settings.
Signed-off-by: Xin Ji <xji@analogixsemi.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20211104033444.2634397-1-xji@analogixsemi.com
Diffstat (limited to 'drivers/gpu/drm/bridge')
0 files changed, 0 insertions, 0 deletions