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authorBen Skeggs <bskeggs@redhat.com>2011-09-17 02:11:39 +1000
committerBen Skeggs <bskeggs@redhat.com>2011-12-21 19:01:13 +1000
commit693461801464eb65eb779261b3d9d80dc9131f81 (patch)
treee5da9ddcfc093b4dbeb07cbc47b9faffc913c23e /drivers/gpu/drm/nouveau/nouveau_pm.h
parent5a4267ab14b392bdf43893c6175b045b5f85d53d (diff)
drm/nv40/pm: convert to new pwm hooks, also fixing pwm type detection
A NV49 appeared a while back that was using the "nv41 style" pwm registers, rather than the "nv40 style" ones my board is using. This disproves the previous theory that the pwm controller choice is chipset-specific. So, after looking at a bunch of vbios images it appears that the next viable theory is that we should select the pwm controller to use based on the gpio line the fan is tied to, just like we do on nv50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_pm.h')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_pm.h6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.h b/drivers/gpu/drm/nouveau/nouveau_pm.h
index 2be384a922b3..5c87afde82d6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.h
@@ -56,10 +56,8 @@ void nv04_pm_clock_set(struct drm_device *, void *);
int nv40_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
void *nv40_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
void nv40_pm_clocks_set(struct drm_device *, void *);
-int nv40_pm_fanspeed_get(struct drm_device *);
-int nv40_pm_fanspeed_set(struct drm_device *, int percent);
-int nv41_pm_fanspeed_get(struct drm_device *);
-int nv41_pm_fanspeed_set(struct drm_device *, int percent);
+int nv40_pm_pwm_get(struct drm_device *, struct dcb_gpio_entry *, u32*, u32*);
+int nv40_pm_pwm_set(struct drm_device *, struct dcb_gpio_entry *, u32, u32);
/* nv50_pm.c */
int nv50_pm_clock_get(struct drm_device *, u32 id);