diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2013-12-02 09:25:54 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-01-23 13:38:56 +1000 |
| commit | 971372eac18294ad31c137503881426b8094550b (patch) | |
| tree | 473f0541246e1c7b63eae773b92edd867bfd4d05 /drivers/gpu/drm/nouveau | |
| parent | db6735cab2b0f12a824f04b1d8fb4da2ea978c8d (diff) | |
drm/nve0/fb: note the memory voltage toggle, not using it yet
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c index ee8ac5ba22c8..1427ae3828d1 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c @@ -101,8 +101,8 @@ nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts) if (!(ram->mr[7] & 0x100)) vr = 0; /* binary driver does this.. bug? */ - ram->mr[7] &= ~0x188; - ram->mr[7] |= (vr & 0x01) << 8; + ram->mr[7] &= ~0x388; + ram->mr[7] |= (vr & 0x03) << 8; ram->mr[7] |= (vh & 0x01) << 7; ram->mr[7] |= (lf & 0x01) << 3; diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index a4c84d6f50e5..e0d63af19107 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c @@ -266,7 +266,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) const u32 ramcfg = ram->base.ramcfg.data; const u32 timing = ram->base.timing.data; int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08); - int mv = 1; /*XXX*/ + int mv = 1; /*XXX: !(nv_ro08(bios, ramcfg + 0x02) & 0x04); */ u32 mask, data, i; ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); @@ -685,7 +685,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) const u32 ramcfg = ram->base.ramcfg.data; const u32 timing = ram->base.timing.data; int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08); - int mv = 1; /*XXX*/ + int mv = 1; /*XXX: !(nv_ro08(bios, ramcfg + 0x02) & 0x04); */ u32 mask, data; ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); |