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| author | Changbin Du <changbin.du@intel.com> | 2017-04-06 10:55:02 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2017-04-12 13:57:42 +0800 |
| commit | e1236bc06c534a97f73e09aed5e1094108553e9f (patch) | |
| tree | 16faf6807220b91820833a47fcc9818a93a46801 /drivers/gpu/drm/omapdrm/omap_irq.c | |
| parent | 0b063bd3ea9c13df78c82aa742e581c39f9d6156 (diff) | |
drm/i915/gvt: Align render mmio list to cacheline
Make the global mmio list be cacheline aligned to improve performance.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm/omap_irq.c')
0 files changed, 0 insertions, 0 deletions