diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-07-07 15:35:06 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-08-04 10:07:37 +0200 |
| commit | 3f4f3b5fede02d338383619ff57744a8415ccceb (patch) | |
| tree | 268bb1b63fe69b8d971a1cae5f5f63093f4b4a6d /drivers/gpu/drm/tegra/sor.c | |
| parent | 054b1bd16138f92cd690324958e48f790a4cd234 (diff) | |
drm/tegra: sor - Configure proper sync polarities
Program the sync signal polarities according to the display mode.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/sor.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/sor.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 479da1b210b4..6cb861bf1e03 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -815,12 +815,22 @@ static int tegra_output_sor_enable(struct tegra_output *output) * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete * raster, associate with display controller) */ - value = SOR_STATE_ASY_VSYNCPOL | - SOR_STATE_ASY_HSYNCPOL | - SOR_STATE_ASY_PROTOCOL_DP_A | + value = SOR_STATE_ASY_PROTOCOL_DP_A | SOR_STATE_ASY_CRC_MODE_COMPLETE | SOR_STATE_ASY_OWNER(dc->pipe + 1); + if (mode->flags & DRM_MODE_FLAG_PHSYNC) + value &= ~SOR_STATE_ASY_HSYNCPOL; + + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + value |= SOR_STATE_ASY_HSYNCPOL; + + if (mode->flags & DRM_MODE_FLAG_PVSYNC) + value &= ~SOR_STATE_ASY_VSYNCPOL; + + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + value |= SOR_STATE_ASY_VSYNCPOL; + switch (config.bits_per_pixel) { case 24: value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; |