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authorJian Jun Chen <jian.jun.chen@intel.com>2017-08-23 13:23:10 +0800
committerZhenyu Wang <zhenyuw@linux.intel.com>2017-09-05 10:26:08 +0800
commitd02fd5f7709f1296bad5d92e7e8515ef1a05dec4 (patch)
treefa8bd59d1f7119f43005aa31753870e0b9b177c9 /drivers/gpu
parenta42894ebb50d831ec0b7ee9bee7f5a5a37bad7e1 (diff)
drm/i915/gvt: Remove one duplicated MMIO
Remove one duplicated MMIO GEN6_PCODE_MAILBOX. Duplicated MMIO will cause host GVT-g initialization failure. Fixes: 9c3a16c887f0 ("drm/i915/hsw+: Add support for multiple power well regs") Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Acked-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 9220a756ecfc..022dbc4a15d6 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2659,7 +2659,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
skl_power_well_ctl_write);
- MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL_PLUS, NULL, mailbox_write);
MMIO_D(0xa210, D_SKL_PLUS);
MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);