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authorSeungwon Jeon <tgih.jun@samsung.com>2014-03-14 21:12:27 +0900
committerChris Ball <chris@printf.net>2014-04-20 16:59:48 -0400
commit5438ad95a57cbfd95708a5047a27ff3cce345b79 (patch)
tree716db308492802ea9df5780b1423aa9bdded00eb /drivers/mmc/host/omap_hsmmc.c
parent6dad6c9594577969f6d74ca1b344e00314bb3b64 (diff)
mmc: omap: clarify DDR timing mode between SD-UHS and eMMC
Replaced UHS_DDR50 with MMC_DDR52. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Acked-by: Balaji T K <balajitk@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'drivers/mmc/host/omap_hsmmc.c')
-rw-r--r--drivers/mmc/host/omap_hsmmc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index e91ee21549d0..b4de63bf10fd 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -582,7 +582,7 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
* - MMC/SD clock coming out of controller > 25MHz
*/
if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
- (ios->timing != MMC_TIMING_UHS_DDR50) &&
+ (ios->timing != MMC_TIMING_MMC_DDR52) &&
((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
regval = OMAP_HSMMC_READ(host->base, HCTL);
if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
@@ -602,7 +602,7 @@ static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
u32 con;
con = OMAP_HSMMC_READ(host->base, CON);
- if (ios->timing == MMC_TIMING_UHS_DDR50)
+ if (ios->timing == MMC_TIMING_MMC_DDR52)
con |= DDR; /* configure in DDR mode */
else
con &= ~DDR;