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authorLinus Torvalds <torvalds@linux-foundation.org>2020-04-02 16:45:46 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2020-04-02 16:45:46 -0700
commite109f506074152b7241bcbd3949a099e776cb802 (patch)
tree19a5c7e07a4f791cf02c060a3a4d370315fe1cfa /drivers/mtd/spi-nor/sst.c
parente964f1e04a1ce562f0d748b29326244d3cb35ba4 (diff)
parent025a06c1104cd8995646b761d117816b5f28c873 (diff)
Merge tag 'mtd/for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal: "MTD core changes: - Fix issue where write_cached_data() fails but write() still returns success - maps: sa1100-flash: Replace zero-length array with flexible-array member - phram: Fix a double free issue in error path - Convert fallthrough comments into statements - MAINTAINERS: Add the IRC channel to the MTD related subsystems Raw NAND core changes: - Add support for manufacturer specific suspend/resume operation - Add support for manufacturer specific lock/unlock operation - Replace zero-length array with flexible-array member - Fix a typo ("manufecturer") - Ensure nand_soft_waitrdy wait period is enough Raw NAND controller driver changes: - Brcmnand: * Add support for flash-edu for dma transfers (+ bindings) - Cadence: * Reinit completion before executing a new command * Change bad block marker size * Fix the calculation of the avaialble OOB size * Get meta data size from registers - Qualcom: * Use dma_request_chan() instead dma_request_slave_channel() * Release resources on failure within qcom_nandc_alloc() - Allwinner: * Use dma_request_chan() instead dma_request_slave_channel() - Marvell: * Use dma_request_chan() instead dma_request_slave_channel() * Release DMA channel on error - Freescale: * Use dma_request_chan() instead dma_request_slave_channel() - Macronix: * Add support for Macronix NAND randomizer (+ bindings) - Ams-delta: * Rename structures and functions to gpio_nand* * Make the driver custom I/O ready * Drop useless local variable * Support custom driver initialisation * Add module device tables * Handle more GPIO pins as optional * Make read pulses optional * Don't hardcode read/write pulse widths * Push inversion handling to gpiolib * Enable OF partition info support * Drop board specific partition info * Use struct gpio_nand_platdata * Write protect device during probe - Ingenic: * Use devm_platform_ioremap_resource() * Add dependency on MIPS || COMPILE_TEST - Denali: * Deassert write protect pin - ST: * Use dma_request_chan() instead dma_request_slave_channel() Raw NAND chip driver changes: - Toshiba: * Support reading the number of bitflips for BENAND (Built-in ECC NAND) - Macronix: * Add support for deep power down mode * Add support for block protection SPI-NAND core changes: - Do not erase the block before writing a bad block marker - Explicitly use MTD_OPS_RAW to write the bad block marker to OOB - Stop using spinand->oobbuf for buffering bad block markers - Rework detect procedure for different READ_ID operation SPI-NAND driver changes: - Toshiba: * Support for new Kioxia Serial NAND * Rename function name to change suffix and prefix (8Gbit) * Add comment about Kioxia ID - Micron: * Add new Micron SPI NAND devices with multiple dies * Add M70A series Micron SPI NAND devices * identify SPI NAND device with Continuous Read mode * Add new Micron SPI NAND devices * Describe the SPI NAND device MT29F2G01ABAGD * Generalize the OOB layout structure and function names SPI NOR core changes: - Move all the manufacturer specific quirks/code out of the core, to make the core logic more readable and thus ease maintenance. - Move the SFDP logic out of the core, it provides a better separation between the SFDP parsing and core logic. - Trim what is exposed in spi-nor.h. The SPI NOR controllers drivers must not be able to use structures that are meant just for the SPI NOR core. - Use the spi-mem direct mapping API to let advanced controllers optimize the read/write operations when they support direct mapping. - Add generic formula for the Status Register block protection handling. It fixes some long standing locking limitations and eases the addition of the 4bit block protection support. - Add block protection support for flashes with 4 block protection bits in the Status Register. SPI NOR controller drivers changes: - The mtk-quadspi driver is replaced by the new spi-mem spi-mtk-nor driver. - Merge tag 'mtk-mtd-spi-move' into spi-nor/next to avoid conflicts. HyperBus changes: - Print error msg when compatible is wrong or missing - Move mapping of direct access window from core to individual drivers" * tag 'mtd/for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (103 commits) mtd: Convert fallthrough comments into statements mtd: rawnand: toshiba: Support reading the number of bitflips for BENAND (Built-in ECC NAND) MAINTAINERS: Add the IRC channel to the MTD related subsystems mtd: Fix issue where write_cached_data() fails but write() still returns success mtd: maps: sa1100-flash: Replace zero-length array with flexible-array member mtd: phram: fix a double free issue in error path mtd: spinand: toshiba: Support for new Kioxia Serial NAND mtd: spinand: toshiba: Rename function name to change suffix and prefix (8Gbit) mtd: rawnand: macronix: Add support for deep power down mode mtd: rawnand: Add support for manufacturer specific suspend/resume operation mtd: spi-nor: Enable locking for n25q512ax3/n25q512a mtd: spi-nor: Add SR 4bit block protection support mtd: spi-nor: Add generic formula for SR block protection handling mtd: spi-nor: Set all BP bits to one when lock_len == mtd->size mtd: spi-nor: controllers: aspeed-smc: Replace zero-length array with flexible-array member mtd: spi-nor: Clear WEL bit when erase or program errors occur MAINTAINERS: update entry after SPI NOR controller move mtd: spi-nor: Trim what is exposed in spi-nor.h mtd: spi-nor: Drop the MFR definitions mtd: spi-nor: Get rid of the now empty spi_nor_ids[] table ...
Diffstat (limited to 'drivers/mtd/spi-nor/sst.c')
-rw-r--r--drivers/mtd/spi-nor/sst.c151
1 files changed, 151 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
new file mode 100644
index 000000000000..e0af6d25d573
--- /dev/null
+++ b/drivers/mtd/spi-nor/sst.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2005, Intec Automation Inc.
+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
+ */
+
+#include <linux/mtd/spi-nor.h>
+
+#include "core.h"
+
+static const struct flash_info sst_parts[] = {
+ /* SST -- large erase sizes are "overlays", "sectors" are 4K */
+ { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8,
+ SECT_4K | SST_WRITE) },
+ { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16,
+ SECT_4K | SST_WRITE) },
+ { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32,
+ SECT_4K | SST_WRITE) },
+ { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64,
+ SECT_4K | SST_WRITE) },
+ { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
+ { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1,
+ SECT_4K | SST_WRITE) },
+ { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2,
+ SECT_4K | SST_WRITE) },
+ { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4,
+ SECT_4K | SST_WRITE) },
+ { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
+ { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
+ { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8,
+ SECT_4K | SST_WRITE) },
+ { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16,
+ SECT_4K | SST_WRITE) },
+ { "sst26wf016b", INFO(0xbf2651, 0, 64 * 1024, 32,
+ SECT_4K | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ) },
+ { "sst26vf016b", INFO(0xbf2641, 0, 64 * 1024, 32,
+ SECT_4K | SPI_NOR_DUAL_READ) },
+ { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128,
+ SECT_4K | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ) },
+};
+
+static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
+ size_t actual = 0;
+ int ret;
+
+ dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
+
+ ret = spi_nor_lock_and_prep(nor);
+ if (ret)
+ return ret;
+
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto out;
+
+ nor->sst_write_second = false;
+
+ /* Start write from odd address. */
+ if (to % 2) {
+ nor->program_opcode = SPINOR_OP_BP;
+
+ /* write one byte. */
+ ret = spi_nor_write_data(nor, to, 1, buf);
+ if (ret < 0)
+ goto out;
+ WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+ goto out;
+
+ to++;
+ actual++;
+ }
+
+ /* Write out most of the data here. */
+ for (; actual < len - 1; actual += 2) {
+ nor->program_opcode = SPINOR_OP_AAI_WP;
+
+ /* write two bytes. */
+ ret = spi_nor_write_data(nor, to, 2, buf + actual);
+ if (ret < 0)
+ goto out;
+ WARN(ret != 2, "While writing 2 bytes written %i bytes\n", ret);
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+ goto out;
+ to += 2;
+ nor->sst_write_second = true;
+ }
+ nor->sst_write_second = false;
+
+ ret = spi_nor_write_disable(nor);
+ if (ret)
+ goto out;
+
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+ goto out;
+
+ /* Write out trailing byte if it exists. */
+ if (actual != len) {
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto out;
+
+ nor->program_opcode = SPINOR_OP_BP;
+ ret = spi_nor_write_data(nor, to, 1, buf + actual);
+ if (ret < 0)
+ goto out;
+ WARN(ret != 1, "While writing 1 byte written %i bytes\n", ret);
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+ goto out;
+
+ actual += 1;
+
+ ret = spi_nor_write_disable(nor);
+ }
+out:
+ *retlen += actual;
+ spi_nor_unlock_and_unprep(nor);
+ return ret;
+}
+
+static void sst_default_init(struct spi_nor *nor)
+{
+ nor->flags |= SNOR_F_HAS_LOCK;
+}
+
+static void sst_post_sfdp_fixups(struct spi_nor *nor)
+{
+ if (nor->info->flags & SST_WRITE)
+ nor->mtd._write = sst_write;
+}
+
+static const struct spi_nor_fixups sst_fixups = {
+ .default_init = sst_default_init,
+ .post_sfdp = sst_post_sfdp_fixups,
+};
+
+const struct spi_nor_manufacturer spi_nor_sst = {
+ .name = "sst",
+ .parts = sst_parts,
+ .nparts = ARRAY_SIZE(sst_parts),
+ .fixups = &sst_fixups,
+};