diff options
| author | Piyush Mehta <piyush.mehta@amd.com> | 2022-09-20 10:52:35 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-09-22 15:52:30 +0200 |
| commit | 63d7f9810a38102cdb8cad214fac98682081e1a7 (patch) | |
| tree | 650010e675ec142c395f04960d3e80d442bf3130 /drivers/net/dsa/microchip/ksz_common.c | |
| parent | 031cba1695d4d3767ba47718077e83f2b5aac944 (diff) | |
usb: dwc3: core: Enable GUCTL1 bit 10 for fixing termination error after resume bug
When configured in HOST mode, after issuing U3/L2 exit controller fails
to send proper CRC checksum in CRC5 field. Because of this behavior
Transaction Error is generated, resulting in reset and re-enumeration of
usb device attached. Enabling chicken bit 10 of GUCTL1 will correct this
problem.
When this bit is set to '1', the UTMI/ULPI opmode will be changed to
"normal" along with HS terminations, term, and xcvr signals after EOR.
This option is to support certain legacy UTMI/ULPI PHYs.
Added "snps,resume-hs-terminations" quirk to resolved the above issue.
Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Link: https://lore.kernel.org/r/20220920052235.194272-3-piyush.mehta@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/net/dsa/microchip/ksz_common.c')
0 files changed, 0 insertions, 0 deletions