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| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-01-22 09:05:34 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-01-22 09:05:34 +0100 |
| commit | c318f074d9fdeae16e19cbb2ed53b50d2bcdfdb8 (patch) | |
| tree | 44c6552fa919dfe1fc681949bf5d81fcf6a2beb8 /drivers/net/phy/dp83867.c | |
| parent | 7b2d7faa09fcbd0184634544f732f4b2da0b20a8 (diff) | |
| parent | def9d2780727cec3313ed3522d0123158d87224d (diff) | |
Merge 5.5-rc7 into staging-next
We want the staging fixes in here as well
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/net/phy/dp83867.c')
| -rw-r--r-- | drivers/net/phy/dp83867.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 9cd9dcee4eb2..01cf71358359 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -97,6 +97,7 @@ #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 #define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14) #define DP83867_PHYCR_RESERVED_MASK BIT(11) +#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf @@ -599,7 +600,12 @@ static int dp83867_phy_reset(struct phy_device *phydev) usleep_range(10, 20); - return 0; + /* After reset FORCE_LINK_GOOD bit is set. Although the + * default value should be unset. Disable FORCE_LINK_GOOD + * for the phy to work properly. + */ + return phy_modify(phydev, MII_DP83867_PHYCTRL, + DP83867_PHYCR_FORCE_LINK_GOOD, 0); } static struct phy_driver dp83867_driver[] = { |