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| author | Akeem G Abodunrin <akeem.g.abodunrin@intel.com> | 2022-04-25 20:53:15 +0530 |
|---|---|---|
| committer | Ramalingam C <ramalingam.c@intel.com> | 2022-05-02 15:18:07 +0530 |
| commit | 7c161b85e88552a037566678128c169fba3b1efe (patch) | |
| tree | 5dbfc2e7bc7b0c59df054e96073f50f416548ca5 /drivers/pcmcia/yenta_socket.c | |
| parent | 59a4752895b2e43351c7c1dd2b264d17d74e8466 (diff) | |
drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing
When bit 19 of MI_LOAD_REGISTER_IMM instruction opcode is set on tgl+
devices, HW does not care about certain register address offsets, but
instead check the following for valid address ranges on specific engines:
RCS && CCS: BITS(0 - 10)
BCS: BITS(0 - 11)
VECS && VCS: BITS(0 - 13)
Also, tgl+ now support relative addressing for BCS engine - So, this
patch fixes issue with live_gt_lrc selftest that is failing where there is
mismatch between LRC register layout generated during init and HW
default register offsets.
Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220425152317.4275-2-ramalingam.c@intel.com
Diffstat (limited to 'drivers/pcmcia/yenta_socket.c')
0 files changed, 0 insertions, 0 deletions