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authorJinZe.Xu <JinZe.Xu@amd.com>2021-05-18 14:36:37 +0800
committerAlex Deucher <alexander.deucher@amd.com>2021-06-08 12:16:14 -0400
commit2259918e087d9967e6c8f9b621d67d5968019724 (patch)
tree374efdd157b35b87d25c756ef7c0dfe72ba3ac23 /drivers
parent346cf627fb27c0fea63a041cedbaa4f31784e504 (diff)
drm/amd/display: Control power gating by driver.
[Why] This disablement would be specific for Nav10 and shouldn’t be propagated to the other programs. [How] Power gating is controlled by driver. Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c34
1 files changed, 12 insertions, 22 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
index e8580cccbebf..0a6d58dd8f6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
@@ -86,17 +86,12 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool po
1, 1000);
break;
case 4: /* DPP4 */
- /*
- * Do not power gate DPP4, should be left at HW default, power on permanently.
- * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard
- * reset.
- * REG_UPDATE(DOMAIN9_PG_CONFIG,
- * DOMAIN9_POWER_GATE, power_gate);
- *
- * REG_WAIT(DOMAIN9_PG_STATUS,
- * DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
- * 1, 1000);
- */
+ REG_UPDATE(DOMAIN9_PG_CONFIG,
+ DOMAIN9_POWER_GATE, power_gate);
+
+ REG_WAIT(DOMAIN9_PG_STATUS,
+ DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
+ 1, 1000);
break;
default:
BREAK_TO_DEBUGGER();
@@ -148,17 +143,12 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool
1, 1000);
break;
case 4: /* DCHUBP4 */
- /*
- * Do not power gate DCHUB4, should be left at HW default, power on permanently.
- * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard
- * reset.
- * REG_UPDATE(DOMAIN8_PG_CONFIG,
- * DOMAIN8_POWER_GATE, power_gate);
- *
- * REG_WAIT(DOMAIN8_PG_STATUS,
- * DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
- * 1, 1000);
- */
+ REG_UPDATE(DOMAIN8_PG_CONFIG,
+ DOMAIN8_POWER_GATE, power_gate);
+
+ REG_WAIT(DOMAIN8_PG_STATUS,
+ DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
+ 1, 1000);
break;
default:
BREAK_TO_DEBUGGER();