diff options
| author | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2021-06-21 12:14:14 -0700 |
|---|---|---|
| committer | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2021-06-21 16:15:29 -0700 |
| commit | 2ef140bd23522f71da83667eee35d53eaafd7659 (patch) | |
| tree | 393967fb33cc27213a24284683f567466ca99775 /drivers | |
| parent | 3d5928a168a9546b23c6b3439c6158d7a028326c (diff) | |
drm/i915/adl_p: Pipe B DMC Support
ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210621191415.29823-4-anusha.srivatsa@intel.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dmc.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 2a1c39a0e56e..db38891a9ef0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused) seq_printf(m, "path: %s\n", dmc->fw_path); seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >= 12)); seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload)); + seq_printf(m, "Pipe B fw support: %s\n", yesno(IS_ALDERLAKE_P(dev_priv))); + seq_printf(m, "Pipe B fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEB].payload)); if (!intel_dmc_has_payload(dev_priv)) goto out; diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h index 007a284b0ef0..c3c00ff03869 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.h +++ b/drivers/gpu/drm/i915/display/intel_dmc.h @@ -19,6 +19,7 @@ struct drm_i915_private; enum { DMC_FW_MAIN = 0, DMC_FW_PIPEA, + DMC_FW_PIPEB, DMC_FW_MAX }; |