diff options
| author | Jitao Shi <jitao.shi@mediatek.com> | 2019-08-11 18:40:04 +0800 |
|---|---|---|
| committer | CK Hu <ck.hu@mediatek.com> | 2019-10-07 12:29:38 +0800 |
| commit | 3c6bd94d32c45d47a0fce49e9cd64d72ff612bb5 (patch) | |
| tree | d107d2ebc75974d629fabfe807d633da7f8dab25 /drivers | |
| parent | 89d0e3f8825822ca20f3af2d61e5e1e6df4c2476 (diff) | |
drm/mediatek: add dsi reg commit disable control
New DSI IP has shadow register and working reg. The register
values are writen to shadow register. And then trigger with
commit reg, the register values will be moved working register.
This function is default on. But this driver doesn't use this
function. So add the disable control.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/mediatek/mtk_dsi.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index a7caf75fb971..881c0afabf17 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -125,6 +125,10 @@ #define VM_CMD_EN BIT(0) #define TS_VFP_EN BIT(5) +#define DSI_SHADOW_DEBUG 0x190U +#define FORCE_COMMIT BIT(0) +#define BYPASS_SHADOW BIT(1) + #define CONFIG (0xff << 0) #define SHORT_PACKET 0 #define LONG_PACKET 2 @@ -151,6 +155,7 @@ struct phy; struct mtk_dsi_driver_data { const u32 reg_cmdq_off; + bool has_shadow_ctl; }; struct mtk_dsi { @@ -588,6 +593,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) } mtk_dsi_enable(dsi); + + if (dsi->driver_data->has_shadow_ctl) + writel(FORCE_COMMIT | BYPASS_SHADOW, + dsi->regs + DSI_SHADOW_DEBUG); + mtk_dsi_reset_engine(dsi); mtk_dsi_phy_timconfig(dsi); |