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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-10-27 11:52:46 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-10-27 11:52:46 +0200
commit6bd5bb1ede67a9681d975c46c55bd8ebaa0926da (patch)
tree26543421726c5911bfd39e05095ab27cf6ad081b /include
parentc929d84735bff4349bde809a5a8eb1996bf371f6 (diff)
parent36914111e6829be36b23d1109214250b5ee1ee9c (diff)
Merge tag 'phy-for-4.15_v1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next
Kishon writes: phy: for 4.15 *) Add support in phy core to perform phy calibration *) Return NULL for optional PHY's even if CONFIG_GENERIC_PHY is not selected *) Add USB Phy driver for Broadcom STB SoCs *) Add support to force mediatek PHY with USB OTG function to enter a specific mode *) Calibrate rockchip-typec PHY according to docs *) Enable dual route feature for sun4i-usb in V3s SoC *) Use dr_mode dt property to enable otg capability in rcar-gen3-usb2 *) Add driver data to specify dedicated otg pins in rcar-gen3-usb2 driver *) Configure the RX equalizer of brcm-sata PHY *) Update pcie phy settings for ti-pipe3 phy *) Add set_mode callback in qcom-ufs-qmp-14nm phy *) Use PHY callbacks in phy-qcom-ufs instead of export APIs Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/phy/phy.h1
-rw-r--r--include/linux/phy/phy-qcom-ufs.h3
-rw-r--r--include/linux/phy/phy.h14
-rw-r--r--include/linux/soc/brcmstb/brcmstb.h17
4 files changed, 31 insertions, 4 deletions
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
index 6c901930eb3e..d16e8755f6a9 100644
--- a/include/dt-bindings/phy/phy.h
+++ b/include/dt-bindings/phy/phy.h
@@ -15,5 +15,6 @@
#define PHY_TYPE_PCIE 2
#define PHY_TYPE_USB2 3
#define PHY_TYPE_USB3 4
+#define PHY_TYPE_UFS 5
#endif /* _DT_BINDINGS_PHY */
diff --git a/include/linux/phy/phy-qcom-ufs.h b/include/linux/phy/phy-qcom-ufs.h
index 35c070ea6ea3..0a2c18a9771d 100644
--- a/include/linux/phy/phy-qcom-ufs.h
+++ b/include/linux/phy/phy-qcom-ufs.h
@@ -31,10 +31,7 @@ void ufs_qcom_phy_enable_dev_ref_clk(struct phy *phy);
*/
void ufs_qcom_phy_disable_dev_ref_clk(struct phy *phy);
-int ufs_qcom_phy_start_serdes(struct phy *phy);
int ufs_qcom_phy_set_tx_lane_enable(struct phy *phy, u32 tx_lanes);
-int ufs_qcom_phy_calibrate_phy(struct phy *phy, bool is_rate_B);
-int ufs_qcom_phy_is_pcs_ready(struct phy *phy);
void ufs_qcom_phy_save_controller_version(struct phy *phy,
u8 major, u16 minor, u16 step);
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e694d4008c4a..4f8423a948d5 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -29,6 +29,8 @@ enum phy_mode {
PHY_MODE_USB_OTG,
PHY_MODE_SGMII,
PHY_MODE_10GKR,
+ PHY_MODE_UFS_HS_A,
+ PHY_MODE_UFS_HS_B,
};
/**
@@ -39,6 +41,7 @@ enum phy_mode {
* @power_off: powering off the phy
* @set_mode: set the mode of the phy
* @reset: resetting the phy
+ * @calibrate: calibrate the phy
* @owner: the module owner containing the ops
*/
struct phy_ops {
@@ -48,6 +51,7 @@ struct phy_ops {
int (*power_off)(struct phy *phy);
int (*set_mode)(struct phy *phy, enum phy_mode mode);
int (*reset)(struct phy *phy);
+ int (*calibrate)(struct phy *phy);
struct module *owner;
};
@@ -141,6 +145,7 @@ int phy_power_on(struct phy *phy);
int phy_power_off(struct phy *phy);
int phy_set_mode(struct phy *phy, enum phy_mode mode);
int phy_reset(struct phy *phy);
+int phy_calibrate(struct phy *phy);
static inline int phy_get_bus_width(struct phy *phy)
{
return phy->attrs.bus_width;
@@ -262,6 +267,13 @@ static inline int phy_reset(struct phy *phy)
return -ENOSYS;
}
+static inline int phy_calibrate(struct phy *phy)
+{
+ if (!phy)
+ return 0;
+ return -ENOSYS;
+}
+
static inline int phy_get_bus_width(struct phy *phy)
{
return -ENOSYS;
@@ -291,7 +303,7 @@ static inline struct phy *devm_phy_get(struct device *dev, const char *string)
static inline struct phy *devm_phy_optional_get(struct device *dev,
const char *string)
{
- return ERR_PTR(-ENOSYS);
+ return NULL;
}
static inline struct phy *devm_of_phy_get(struct device *dev,
diff --git a/include/linux/soc/brcmstb/brcmstb.h b/include/linux/soc/brcmstb/brcmstb.h
index 337ce414e898..8baafd6908b9 100644
--- a/include/linux/soc/brcmstb/brcmstb.h
+++ b/include/linux/soc/brcmstb/brcmstb.h
@@ -1,10 +1,27 @@
#ifndef __BRCMSTB_SOC_H
#define __BRCMSTB_SOC_H
+static inline u32 BRCM_ID(u32 reg)
+{
+ return reg >> 28 ? reg >> 16 : reg >> 8;
+}
+
+static inline u32 BRCM_REV(u32 reg)
+{
+ return reg & 0xff;
+}
+
/*
* Bus Interface Unit control register setup, must happen early during boot,
* before SMP is brought up, called by machine entry point.
*/
void brcmstb_biuctrl_init(void);
+/*
+ * Helper functions for getting family or product id from the
+ * SoC driver.
+ */
+u32 brcmstb_get_family_id(void);
+u32 brcmstb_get_product_id(void);
+
#endif /* __BRCMSTB_SOC_H */