diff options
| author | Archana Patni <archana.patni@intel.com> | 2020-04-21 14:10:19 +0530 |
|---|---|---|
| committer | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2020-05-05 15:32:41 +0300 |
| commit | e87fa339d413c540c065c280ba9e7cc9a8dbcfd1 (patch) | |
| tree | 3a850b872b418be3416c81d0dbc35011a5dd3889 /kernel/gcov/clang.c | |
| parent | f585c9d5436a2dbedcd6c581bcabd41d7e372e21 (diff) | |
platform/x86: intel_pmc_core: Change Jasper Lake S0ix debug reg map back to ICL
Jasper Lake uses Icelake PCH IPs and the S0ix debug interfaces are same as
Icelake. It uses SLP_S0_DBG register latch/read interface from Icelake
generation. It doesn't use Tiger Lake LPM debug registers. Change the
Jasper Lake S0ix debug interface to use the ICL reg map.
Fixes: 16292bed9c56 ("platform/x86: intel_pmc_core: Add Atom based Jasper Lake (JSL) platform support")
Signed-off-by: Archana Patni <archana.patni@intel.com>
Acked-by: David E. Box <david.e.box@intel.com>
Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'kernel/gcov/clang.c')
0 files changed, 0 insertions, 0 deletions