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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-07-15 10:40:50 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-07-15 10:40:50 -0700 |
| commit | 9b59ec8d50a1f28747ceff9a4f39af5deba9540e (patch) | |
| tree | bb51d6c7142e6d471b34e1f1002fbe215b6d64b3 /lib/mpi/mpi-add.c | |
| parent | a8ebfcd33caf29592957229c8350f67b48b8efce (diff) | |
| parent | 7fccd723912702acfc2d75e8f0596982534f7f24 (diff) | |
Merge tag 'riscv-for-linus-5.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
- A fix to avoid printing a warning when modules do not exercise any
errata-dependent behavior and the SiFive errata are enabled.
- A fix to the Microchip PFSOC to attach the L2 cache to the CPU nodes.
* tag 'riscv-for-linus-5.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: don't warn for sifive erratas in modules
riscv: dts: microchip: hook up the mpfs' l2cache
Diffstat (limited to 'lib/mpi/mpi-add.c')
0 files changed, 0 insertions, 0 deletions