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authorMatt Roper <matthew.d.roper@intel.com>2021-07-29 09:59:54 -0700
committerMatt Roper <matthew.d.roper@intel.com>2021-08-05 08:06:01 -0700
commit1705f22c86fb2654df22169c020d9d4ff193e47b (patch)
tree29b520dc81f0b5537b64135c5d2cf8b0a254fd4d /lib/mpi/mpi-sub-ui.c
parent768fe28dd3dcea517d3c491cfe1b5cd768ee1334 (diff)
drm/i915/dg2: Update steering tables
DG2's replicated register ranges are almost the same at XeHP SDV with the exception of one LNCF sub-range that switches to gslice steering. We can re-use the XeHP SDV mslice steering table and just provide a DG2-specific LNCF steering table. Bspec: 66534 Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210729170008.2836648-5-matthew.d.roper@intel.com
Diffstat (limited to 'lib/mpi/mpi-sub-ui.c')
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