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| author | Maxim Mikityanskiy <maximmi@nvidia.com> | 2022-09-27 13:36:04 -0700 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2022-09-28 19:36:36 -0700 |
| commit | 21a0502d59109792b830b476f73287573981a0dd (patch) | |
| tree | 336e4f48312ccdffdccd0c1d97d94fcaaf620043 /lib/ts_fsm.c | |
| parent | e3c4c496dc9a44412bae6e1c5a9cf7fd0cdafba1 (diff) | |
net/mlx5e: Use the aligned max TX MPWQE size
TX MPWQE size is limited to the cacheline-aligned maximum. Use the same
value for the stop room and the capability check.
Signed-off-by: Maxim Mikityanskiy <maximmi@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'lib/ts_fsm.c')
0 files changed, 0 insertions, 0 deletions