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authorWolfram Sang <wsa+renesas@sang-engineering.com>2020-11-10 15:20:57 +0100
committerUlf Hansson <ulf.hansson@linaro.org>2020-11-16 12:48:19 +0100
commitd14ac691bb6f6ebaa7eeec21ca04dd47300ff5b6 (patch)
tree2e7e8d46d158b9aebddf534d5f13d305f82953cd /net/lapb/lapb_timer.c
parentb161d87dfd3d9f3fb064a089a9e521d0e5d3e38f (diff)
mmc: renesas_sdhi: populate SCC pointer at the proper place
The SCC pointer is currently filled whenever the SoC is Gen2+. This is wrong because there is a Gen2-variant without SCC (SDHI_VER_GEN2_SDR50). We have been lucky because the writes to unintended registers have not caused problems so far. But further refactoring work exposed the problem. So, move the pointer initialization to the place where we know that the SDHI instance supports tuning. And also populate the 'reset' pointer unconditionally to make sure the interrupt enable register is always properly set for Gen2+. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201110142058.36393-4-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'net/lapb/lapb_timer.c')
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