diff options
| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2019-07-17 19:06:19 +0100 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2019-07-29 15:49:55 +0300 |
| commit | 0bbfdce345c8cf01a3a985fa99fefd2146dcc748 (patch) | |
| tree | 0c75e39a95312047cc531e677521fe1761ec6136 /scripts/gdb/linux/config.py | |
| parent | 6d61f716a01ec0e134de38ae97e71d6fec5a6ff6 (diff) | |
drm/i915: Fix GEN8_MCR_SELECTOR programming
fls returns bit positions starting from one for the lsb and the MCR
register expects zero based (sub)slice addressing.
Incorrent MCR programming can have the effect of directing MMIO reads of
registers in the 0xb100-0xb3ff range to invalid subslice returning zeroes
instead of actual content.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads")
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190717180624.20354-2-tvrtko.ursulin@linux.intel.com
(cherry picked from commit 15160879d47213c32f357bc67b6014d9aaf14ed7)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'scripts/gdb/linux/config.py')
0 files changed, 0 insertions, 0 deletions