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| author | Huang Rui <ray.huang@amd.com> | 2021-12-24 09:04:56 +0800 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2021-12-30 18:51:17 +0100 |
| commit | 89aa94b4a218339b08f052a28c55322d5a13fc9e (patch) | |
| tree | 99eb9e4b1a3a6c5b7f7663f849d4d7e10f031842 /scripts/gdb/linux/device.py | |
| parent | d341db8f48ea43314f489921962c7f8f4ec27239 (diff) | |
x86/msr: Add AMD CPPC MSR definitions
AMD CPPC (Collaborative Processor Performance Control) function uses MSR
registers to manage the performance hints. So add the MSR register macro
here.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'scripts/gdb/linux/device.py')
0 files changed, 0 insertions, 0 deletions