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| author | Jinzhou Su <Jinzhou.Su@amd.com> | 2021-12-24 09:04:59 +0800 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2021-12-30 18:51:39 +0100 |
| commit | fb0b00af04d083770d6e2762b2838357519f7d2d (patch) | |
| tree | ac32933f24ef0a463f6e620343a7b4ba40482f6f /scripts/gdb/linux/device.py | |
| parent | 2aeca6bd02776d7f56a49a32be0dd184f204d888 (diff) | |
ACPI: CPPC: Add CPPC enable register function
Add a new function to enable CPPC feature. This function
will write Continuous Performance Control package
EnableRegister field on the processor.
CPPC EnableRegister register described in section 8.4.7.1 of ACPI 6.4:
This element is optional. If supported, contains a resource descriptor
with a single Register() descriptor that describes a register to which
OSPM writes a One to enable CPPC on this processor. Before this register
is set, the processor will be controlled by legacy mechanisms (ACPI
Pstates, firmware, etc.).
This register will be used for AMD processors to enable AMD P-State
function instead of legacy ACPI P-States.
Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'scripts/gdb/linux/device.py')
0 files changed, 0 insertions, 0 deletions