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| author | Dinh Nguyen <dinguyen@kernel.org> | 2020-07-31 10:26:40 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2020-08-17 09:07:04 -0500 |
| commit | 0ff5a4812be4ebd4782bbb555d369636eea164f7 (patch) | |
| tree | d44c742722e0e0a9a59958df831c4f6a90c34e2e /scripts/gdb/linux/lists.py | |
| parent | 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 (diff) | |
ARM: dts: socfpga: fix register entry for timer3 on Arria10
Fixes the register address for the timer3 entry on Arria10.
Fixes: 475dc86d08de4 ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/lists.py')
0 files changed, 0 insertions, 0 deletions