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| author | Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> | 2019-09-26 16:20:58 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2019-10-15 15:41:55 +0530 |
| commit | 6c6de1ddb1be3840f2ed5cc9d009a622720940c9 (patch) | |
| tree | b9cb177077ccc1d3c1c3aed675d68c96d8860b4b /scripts/gdb/linux/lists.py | |
| parent | 68fe2b520cee829ed518b4b1f64d2a557bcbffe1 (diff) | |
dmaengine: xilinx_dma: Fix control reg update in vdma_channel_set_config
In vdma_channel_set_config clear the delay, frame count and master mask
before updating their new values. It avoids programming incorrect state
when input parameters are different from default.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/1569495060-18117-3-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/lists.py')
0 files changed, 0 insertions, 0 deletions